diff options
Diffstat (limited to 'tests/ports/stm32/uart.py')
| -rw-r--r-- | tests/ports/stm32/uart.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/ports/stm32/uart.py b/tests/ports/stm32/uart.py index 53b0ea6ade..28eb2261b7 100644 --- a/tests/ports/stm32/uart.py +++ b/tests/ports/stm32/uart.py @@ -1,5 +1,11 @@ +import sys from pyb import UART +if "STM32WB" in sys.implementation._machine: + # UART(1) is usually connected to the REPL on these MCUs. + print("SKIP") + raise SystemExit + # test we can correctly create by id for bus in (-1, 0, 1, 2, 5, 6): try: |