3 files changed, 59 insertions, 16 deletions
diff --git a/tests/extmod_hardware/machine_uart_irq_rx.py b/tests/extmod_hardware/machine_uart_irq_rx.py
index ecc95e62ae..3602c260e3 100644
--- a/tests/extmod_hardware/machine_uart_irq_rx.py
+++ b/tests/extmod_hardware/machine_uart_irq_rx.py
@@ -24,9 +24,14 @@ elif "esp32" in sys.platform:
     tx_pin = 4
     rx_pin = 5
 elif "pyboard" in sys.platform:
-    uart_id = 4
-    tx_pin = None  # PA0
-    rx_pin = None  # PA1
+    if "STM32WB" in sys.implementation._machine:
+        # LPUART(1) is on PA2/PA3
+        uart_id = "LP1"
+    else:
+        # UART(4) is on PA0/PA1
+        uart_id = 4
+    tx_pin = None
+    rx_pin = None
 elif "samd" in sys.platform and "ItsyBitsy M0" in sys.implementation._machine:
     uart_id = 0
     tx_pin = "D1"
diff --git a/tests/extmod_hardware/machine_uart_irq_rxidle.py b/tests/extmod_hardware/machine_uart_irq_rxidle.py
index af2412c75e..3c743c9e0c 100644
--- a/tests/extmod_hardware/machine_uart_irq_rxidle.py
+++ b/tests/extmod_hardware/machine_uart_irq_rxidle.py
@@ -13,6 +13,9 @@ except (ImportError, AttributeError):
 
 import time, sys
 
+# Target tuning options.
+tune_wait_initial_rxidle = False
+
 # Configure pins based on the target.
 if "alif" in sys.platform:
     uart_id = 1
@@ -26,9 +29,15 @@ elif "mimxrt" in sys.platform:
     uart_id = 1
     tx_pin = None
 elif "pyboard" in sys.platform:
-    uart_id = 4
-    tx_pin = None  # PA0
-    rx_pin = None  # PA1
+    tune_wait_initial_rxidle = True
+    if "STM32WB" in sys.implementation._machine:
+        # LPUART(1) is on PA2/PA3
+        uart_id = "LP1"
+    else:
+        # UART(4) is on PA0/PA1
+        uart_id = 4
+    tx_pin = None
+    rx_pin = None
 elif "renesas-ra" in sys.platform:
     uart_id = 9
     tx_pin = None  # P602 @ RA6M2
@@ -55,20 +64,31 @@ def irq(u):
     print("IRQ_RXIDLE:", bool(u.irq().flags() & u.IRQ_RXIDLE), "data:", u.read())
 
 
-text = "12345678"
+text = ("12345678", "abcdefgh")
 
 # Test that the IRQ is called for each set of byte received.
 for bits_per_s in (2400, 9600, 115200):
+    print("========")
+    print("bits_per_s:", bits_per_s)
+
     if tx_pin is None:
         uart = UART(uart_id, bits_per_s)
     else:
         uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
 
+    # Ignore a possible initial RXIDLE condition after creating UART.
+    if tune_wait_initial_rxidle:
+        uart.irq(lambda _: None, uart.IRQ_RXIDLE)
+        time.sleep_ms(10)
+
+    # Configure desired IRQ.
     uart.irq(irq, uart.IRQ_RXIDLE)
 
-    print("write", bits_per_s)
-    uart.write(text)
-    uart.flush()
-    print("ready")
-    time.sleep_ms(100)
-    print("done")
+    for i in range(2):
+        # Write data and wait for IRQ.
+        print("write")
+        uart.write(text[i])
+        uart.flush()
+        print("ready")
+        time.sleep_ms(100)
+        print("done")
diff --git a/tests/extmod_hardware/machine_uart_irq_rxidle.py.exp b/tests/extmod_hardware/machine_uart_irq_rxidle.py.exp
index ce1890a06a..f3c7497e4c 100644
--- a/tests/extmod_hardware/machine_uart_irq_rxidle.py.exp
+++ b/tests/extmod_hardware/machine_uart_irq_rxidle.py.exp
@@ -1,12 +1,30 @@
-write 2400
+========
+bits_per_s: 2400
+write
 ready
 IRQ_RXIDLE: True data: b'12345678'
 done
-write 9600
+write
+ready
+IRQ_RXIDLE: True data: b'abcdefgh'
+done
+========
+bits_per_s: 9600
+write
 ready
 IRQ_RXIDLE: True data: b'12345678'
 done
-write 115200
+write
+ready
+IRQ_RXIDLE: True data: b'abcdefgh'
+done
+========
+bits_per_s: 115200
+write
 ready
 IRQ_RXIDLE: True data: b'12345678'
 done
+write
+ready
+IRQ_RXIDLE: True data: b'abcdefgh'
+done