diff options
Diffstat (limited to 'stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h')
| -rw-r--r-- | stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h | 850 |
1 files changed, 697 insertions, 153 deletions
diff --git a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h b/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h index 1249282a4c..3af7f21567 100644 --- a/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h +++ b/stmhal/hal/f7/inc/stm32f7xx_hal_rcc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.0.1 - * @date 25-June-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -60,12 +60,41 @@ */ /** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. + This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +}RCC_PLLInitTypeDef; + +/** * @brief PLLI2S Clock structure definition */ typedef struct { uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 49 and Max_Data = 432. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. @@ -76,9 +105,12 @@ typedef struct This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLI2S is selected as Clock Source SAI */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. - This parameter must be a number between 0 and 3 for respective values 2, 4, 6 and 8. - This parameter will be used only when PLLI2S is selected as Clock Source SPDDIF-RX */ + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ }RCC_PLLI2SInitTypeDef; /** @@ -87,19 +119,22 @@ typedef struct typedef struct { uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 49 and Max_Data = 432. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. - This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider This parameter will be used only when PLLSAI is disabled */ }RCC_PLLSAIInitTypeDef; @@ -191,6 +226,16 @@ typedef struct uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source + This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ + + uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ + + uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ }RCC_PeriphCLKInitTypeDef; /** * @} @@ -204,45 +249,63 @@ typedef struct /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection * @{ */ -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) -#if defined(STM32F756xx) || defined(STM32F746xx) -#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008) -#endif /* STM32F756xx || STM32F746xx */ -#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400) -#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800) -#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000) -#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000) -#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000) -#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000) -#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000) -#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000) -#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000) -#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000) +#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) +#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) +#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) +#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) +#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) +#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) +#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) +#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) +#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) +#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) +#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) +#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) +#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) +#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) +#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) +#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) +#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) +#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider + * @{ + */ +#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) /** * @} */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider * @{ */ -#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000) -#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001) -#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002) -#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003) +#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) /** * @} */ @@ -250,7 +313,7 @@ typedef struct /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR * @{ */ -#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000) +#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR @@ -261,7 +324,7 @@ typedef struct /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source * @{ */ -#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000) +#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC /** @@ -272,10 +335,12 @@ typedef struct /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source * @{ */ -#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 - +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -283,18 +348,12 @@ typedef struct /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source * @{ */ -#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000) +#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 -/** - * @} - */ - -/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source - * @{ - */ -#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000) -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -302,7 +361,7 @@ typedef struct /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source * @{ */ -#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000) +#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ /** * @} @@ -311,7 +370,7 @@ typedef struct /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source * @{ */ -#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000) +#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL @@ -322,7 +381,7 @@ typedef struct /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source * @{ */ -#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL @@ -333,7 +392,7 @@ typedef struct /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source * @{ */ -#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL @@ -344,7 +403,7 @@ typedef struct /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source * @{ */ -#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL @@ -355,7 +414,7 @@ typedef struct /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source * @{ */ -#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL @@ -366,7 +425,7 @@ typedef struct /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source * @{ */ -#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000) +#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL @@ -377,7 +436,7 @@ typedef struct /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source * @{ */ -#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL @@ -388,7 +447,7 @@ typedef struct /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source * @{ */ -#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL @@ -399,7 +458,7 @@ typedef struct /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source * @{ */ -#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 /** @@ -409,7 +468,7 @@ typedef struct /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source * @{ */ -#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 @@ -420,7 +479,7 @@ typedef struct /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source * @{ */ -#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 /** @@ -430,18 +489,17 @@ typedef struct /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source * @{ */ -#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 /** * @} */ - /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source * @{ */ -#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) +#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL @@ -453,7 +511,7 @@ typedef struct /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source * @{ */ -#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000) +#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL /** * @} @@ -462,14 +520,61 @@ typedef struct /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection * @{ */ -#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000) +#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE +/** + * @} + */ +/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source + * @{ + */ +#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL +/** + * @} + */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source + * @{ + */ +#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /** * @} */ +/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL +/** + * @} + */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) +/** + * @} + */ +#endif /* STM32F769xx || STM32F779xx */ + /** * @} */ @@ -710,6 +815,17 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ @@ -724,16 +840,14 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ UNUSED(tmpreg); \ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ } while(0) #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_DISABLE();\ - }while(0) -#if defined(STM32F756xx) +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -752,7 +866,8 @@ typedef struct #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F756x */ +#endif /* STM32F756x || STM32F777xx || STM32F779xx */ + /** @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before @@ -862,6 +977,24 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ @@ -1008,6 +1141,10 @@ typedef struct #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) +#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) @@ -1063,6 +1200,16 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ @@ -1167,7 +1314,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ @@ -1175,16 +1322,47 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) @@ -1194,9 +1372,17 @@ typedef struct #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ @@ -1259,7 +1445,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) /** * @brief Disable ETHERNET clock. @@ -1270,7 +1456,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) /** @brief Get the enable or disable status of the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1281,17 +1467,21 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) - #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) -#endif /* STM32F756x */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1319,6 +1509,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) +#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) @@ -1347,6 +1541,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) +#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) @@ -1387,9 +1585,17 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) @@ -1407,9 +1613,17 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -1455,31 +1669,35 @@ typedef struct /** @brief Force or release AHB2 peripheral reset. */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) - #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) -#if defined(STM32F756xx) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) +#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** @brief Force or release AHB3 peripheral reset */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) @@ -1495,6 +1713,9 @@ typedef struct #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) @@ -1523,6 +1744,9 @@ typedef struct #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) @@ -1558,9 +1782,9 @@ typedef struct #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) @@ -1577,9 +1801,24 @@ typedef struct #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) + +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -1656,19 +1895,24 @@ typedef struct #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1698,6 +1942,10 @@ typedef struct #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) @@ -1726,6 +1974,10 @@ typedef struct #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) @@ -1741,8 +1993,8 @@ typedef struct #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1767,9 +2019,9 @@ typedef struct #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) @@ -1788,9 +2040,22 @@ typedef struct #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) + +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ @@ -1871,19 +2136,24 @@ typedef struct #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) +#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) -#if defined(STM32F756xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) -#endif /* STM32F756xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1913,6 +2183,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) @@ -1941,6 +2215,10 @@ typedef struct #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) @@ -1982,9 +2260,17 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) @@ -2003,13 +2289,92 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} */ +/*------------------------------- PLL Configuration --------------------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * @param __PLLR__: specifies the division factor for DSI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ + ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ + ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \ + ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR)))) +#else +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ + (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ + ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ + ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ + ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /*---------------------------------------------------------------------------------------------*/ /** @brief Macro to configure the Timers clocks prescalers @@ -2025,8 +2390,8 @@ typedef struct * to division by 8 or more. */ #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ - RCC->DCKCFGR1 |= (__PRESC__);\ - }while(0) + RCC->DCKCFGR1 |= (__PRESC__); \ + }while(0) /** @brief Macros to Enable or Disable the PLLISAI. * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. @@ -2039,36 +2404,44 @@ typedef struct * @note PLLSAI clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. - * This parameter must be a number between Min_Data = 49 and Max_Data = 432. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 49 and Max_Data = 432 MHz. + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. * @param __PLLSAIQ__: specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLSAIR__: specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks - * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider . */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28)) +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\ + ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\ + ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\ + ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))) -/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. +/** @brief Macro to configure the PLLI2S clock multiplication and division factors. * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API) * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. - * This parameter must be a number between Min_Data = 192 and Max_Data = 432. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock. + * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. * @param __PLLI2SQ__: specifies the division factor for SAI clock. * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLI2SR__: specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. - * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock. - * This parameter can be a number between 0 and 3 for respective values 2, 4, 6 and 8 */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28)) +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ + ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\ + ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ + ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. * @note This function must be called before enabling the PLLI2S. @@ -2090,7 +2463,7 @@ typedef struct * * @note This function must be called before enabling the PLLSAI. * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . - * This parameter must be a number between Min_Data = 2 and Max_Data = 16. + * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ @@ -2107,6 +2480,9 @@ typedef struct * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) @@ -2119,6 +2495,9 @@ typedef struct * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) @@ -2134,6 +2513,9 @@ typedef struct * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) @@ -2147,6 +2529,9 @@ typedef struct * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) @@ -2450,7 +2835,7 @@ typedef struct * @param __CEC_CLKSOURCE__: specifies the CEC clock source. * This parameter can be one of the following values: * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock - * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock */ #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) @@ -2467,7 +2852,7 @@ typedef struct * @param __CLK48_SOURCE__: specifies the CLK48 clock source. * This parameter can be one of the following values: * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source - * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 selected as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source */ #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) @@ -2475,7 +2860,7 @@ typedef struct /** @brief macro to get the CLK48 source. * @retval The clock source can be one of the following values: * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source - * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 used as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source */ #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) @@ -2496,6 +2881,72 @@ typedef struct */ #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). + * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) + +/** @brief macro to get the SDMMC2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) + +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock + * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock + */ +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock + */ +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) + +/** @brief Macro to configure the DFSDM1 Audio clock + * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 Audio clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__: specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) +#endif /* STM32F769xx || STM32F779xx */ /** * @} */ @@ -2520,7 +2971,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); */ #if defined(STM32F756xx) || defined(STM32F746xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ @@ -2540,12 +2991,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32F745xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ @@ -2564,17 +3015,78 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#endif /* STM32F756xx || STM32F746xx */ -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8)) +#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F765xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32F746xx || STM32F756xx */ +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ + ((VALUE) == RCC_PLLI2SP_DIV4) ||\ + ((VALUE) == RCC_PLLI2SP_DIV6) ||\ + ((VALUE) == RCC_PLLI2SP_DIV8)) #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLSAIP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8)) +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) @@ -2583,20 +3095,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ - ((VALUE) == RCC_PLLSAIDIVR_4) ||\ - ((VALUE) == RCC_PLLSAIDIVR_8) ||\ + ((VALUE) == RCC_PLLSAIDIVR_4) ||\ + ((VALUE) == RCC_PLLSAIDIVR_8) ||\ ((VALUE) == RCC_PLLSAIDIVR_16)) #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) -#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) -#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) + ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) -#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) +#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ ((SOURCE) == RCC_CECCLKSOURCE_LSE)) @@ -2674,6 +3180,44 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); #define IS_RCC_TIMPRES(VALUE) \ (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ ((VALUE) == RCC_TIMPRES_ACTIVATED)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) + +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) + +#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) + +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \ + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ + ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /** * @} */ |