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-rw-r--r--py/emitnative.c99
1 files changed, 27 insertions, 72 deletions
diff --git a/py/emitnative.c b/py/emitnative.c
index 4b470f3c93..7662de69e2 100644
--- a/py/emitnative.c
+++ b/py/emitnative.c
@@ -1537,12 +1537,10 @@ static void emit_native_load_subscr(emit_t *emit) {
switch (vtype_base) {
case VTYPE_PTR8: {
// pointer to 8-bit memory
- #if N_THUMB
- if (index_value >= 0 && index_value < 32) {
- asm_thumb_ldrb_rlo_rlo_i5(emit->as, REG_RET, reg_base, index_value);
- break;
- }
- #elif N_RV32
+ #ifdef ASM_LOAD8_REG_REG_OFFSET
+ ASM_LOAD8_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value);
+ #else
+ #if N_RV32
if (FIT_SIGNED(index_value, 12)) {
asm_rv32_opcode_lbu(emit->as, REG_RET, reg_base, index_value);
break;
@@ -1561,26 +1559,14 @@ static void emit_native_load_subscr(emit_t *emit) {
reg_base = reg_index;
}
ASM_LOAD8_REG_REG(emit->as, REG_RET, reg_base); // load from (base+index)
+ #endif
break;
}
case VTYPE_PTR16: {
// pointer to 16-bit memory
- #if N_THUMB
- if (index_value >= 0 && index_value < 32) {
- asm_thumb_ldrh_rlo_rlo_i5(emit->as, REG_RET, reg_base, index_value);
- break;
- }
- #elif N_RV32
- if (FIT_SIGNED(index_value, 11)) {
- asm_rv32_opcode_lhu(emit->as, REG_RET, reg_base, index_value << 1);
- break;
- }
- #elif N_XTENSA || N_XTENSAWIN
- if (index_value >= 0 && index_value < 256) {
- asm_xtensa_op_l16ui(emit->as, REG_RET, reg_base, index_value);
- break;
- }
- #endif
+ #ifdef ASM_LOAD16_REG_REG_OFFSET
+ ASM_LOAD16_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value);
+ #else
if (index_value != 0) {
// index is a non-zero immediate
need_reg_single(emit, reg_index, 0);
@@ -1589,26 +1575,14 @@ static void emit_native_load_subscr(emit_t *emit) {
reg_base = reg_index;
}
ASM_LOAD16_REG_REG(emit->as, REG_RET, reg_base); // load from (base+2*index)
+ #endif
break;
}
case VTYPE_PTR32: {
// pointer to 32-bit memory
- #if N_THUMB
- if (index_value >= 0 && index_value < 32) {
- asm_thumb_ldr_rlo_rlo_i5(emit->as, REG_RET, reg_base, index_value);
- break;
- }
- #elif N_RV32
- if (FIT_SIGNED(index_value, 10)) {
- asm_rv32_opcode_lw(emit->as, REG_RET, reg_base, index_value << 2);
- break;
- }
- #elif N_XTENSA || N_XTENSAWIN
- if (index_value >= 0 && index_value < 256) {
- asm_xtensa_l32i_optimised(emit->as, REG_RET, reg_base, index_value);
- break;
- }
- #endif
+ #ifdef ASM_LOAD32_REG_REG_OFFSET
+ ASM_LOAD32_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value);
+ #else
if (index_value != 0) {
// index is a non-zero immediate
need_reg_single(emit, reg_index, 0);
@@ -1617,6 +1591,7 @@ static void emit_native_load_subscr(emit_t *emit) {
reg_base = reg_index;
}
ASM_LOAD32_REG_REG(emit->as, REG_RET, reg_base); // load from (base+4*index)
+ #endif
break;
}
default:
@@ -1809,13 +1784,10 @@ static void emit_native_store_subscr(emit_t *emit) {
switch (vtype_base) {
case VTYPE_PTR8: {
// pointer to 8-bit memory
- // TODO optimise to use thumb strb r1, [r2, r3]
- #if N_THUMB
- if (index_value >= 0 && index_value < 32) {
- asm_thumb_strb_rlo_rlo_i5(emit->as, reg_value, reg_base, index_value);
- break;
- }
- #elif N_RV32
+ #ifdef ASM_STORE8_REG_REG_OFFSET
+ ASM_STORE8_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value);
+ #else
+ #if N_RV32
if (FIT_SIGNED(index_value, 12)) {
asm_rv32_opcode_sb(emit->as, reg_value, reg_base, index_value);
break;
@@ -1837,16 +1809,15 @@ static void emit_native_store_subscr(emit_t *emit) {
reg_base = reg_index;
}
ASM_STORE8_REG_REG(emit->as, reg_value, reg_base); // store value to (base+index)
+ #endif
break;
}
case VTYPE_PTR16: {
// pointer to 16-bit memory
- #if N_THUMB
- if (index_value >= 0 && index_value < 32) {
- asm_thumb_strh_rlo_rlo_i5(emit->as, reg_value, reg_base, index_value);
- break;
- }
- #elif N_RV32
+ #ifdef ASM_STORE16_REG_REG_OFFSET
+ ASM_STORE16_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value);
+ #else
+ #if N_RV32
if (FIT_SIGNED(index_value, 11)) {
asm_rv32_opcode_sh(emit->as, reg_value, reg_base, index_value << 1);
break;
@@ -1864,38 +1835,22 @@ static void emit_native_store_subscr(emit_t *emit) {
reg_base = reg_index;
}
ASM_STORE16_REG_REG(emit->as, reg_value, reg_base); // store value to (base+2*index)
+ #endif
break;
}
case VTYPE_PTR32: {
// pointer to 32-bit memory
- #if N_THUMB
- if (index_value >= 0 && index_value < 32) {
- asm_thumb_str_rlo_rlo_i5(emit->as, reg_value, reg_base, index_value);
- break;
- }
- #elif N_RV32
- if (FIT_SIGNED(index_value, 10)) {
- asm_rv32_opcode_sw(emit->as, reg_value, reg_base, index_value << 2);
- break;
- }
- #elif N_XTENSA || N_XTENSAWIN
- if (index_value >= 0 && index_value < 256) {
- asm_xtensa_s32i_optimised(emit->as, reg_value, reg_base, index_value);
- break;
- }
- #endif
+ #ifdef ASM_STORE32_REG_REG_OFFSET
+ ASM_STORE32_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value);
+ #else
if (index_value != 0) {
// index is a non-zero immediate
- #if N_ARM
- ASM_MOV_REG_IMM(emit->as, reg_index, index_value);
- asm_arm_str_reg_reg_reg(emit->as, reg_value, reg_base, reg_index);
- break;
- #endif
ASM_MOV_REG_IMM(emit->as, reg_index, index_value << 2);
ASM_ADD_REG_REG(emit->as, reg_index, reg_base); // add 4*index to base
reg_base = reg_index;
}
ASM_STORE32_REG_REG(emit->as, reg_value, reg_base); // store value to (base+4*index)
+ #endif
break;
}
default: