diff options
| -rw-r--r-- | ports/stm32/Makefile | 2 | ||||
| -rw-r--r-- | ports/stm32/flashbdev.c | 248 | ||||
| -rw-r--r-- | ports/stm32/spibdev.c | 78 | ||||
| -rw-r--r-- | ports/stm32/storage.c | 333 | ||||
| -rw-r--r-- | ports/stm32/storage.h | 11 |
5 files changed, 376 insertions, 296 deletions
diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 55ccafe766..1ef303cd4b 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -232,6 +232,8 @@ SRC_C = \ rng.c \ rtc.c \ flash.c \ + flashbdev.c \ + spibdev.c \ storage.c \ sdcard.c \ fatfs_port.c \ diff --git a/ports/stm32/flashbdev.c b/ports/stm32/flashbdev.c new file mode 100644 index 0000000000..49fe5c6964 --- /dev/null +++ b/ports/stm32/flashbdev.c @@ -0,0 +1,248 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2018 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdint.h> +#include <string.h> + +#include "py/obj.h" +#include "systick.h" +#include "led.h" +#include "flash.h" +#include "storage.h" + +#if !defined(MICROPY_HW_SPIFLASH_SIZE_BITS) + +// Here we try to automatically configure the location and size of the flash +// pages to use for the internal storage. We also configure the location of the +// cache used for writing. + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) + +#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k +#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of CCM +#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (224) // sectors 1,2,3,4: 16k+16k+16k+64k=112k + +// enable this to get an extra 64k of storage (uses the last sector of the flash) +#if 0 +#define FLASH_MEM_SEG2_START_ADDR (0x080e0000) // sector 11 +#define FLASH_MEM_SEG2_NUM_BLOCKS (128) // sector 11: 128k +#endif + +#elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + +STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k +#define CACHE_MEM_START_ADDR (&flash_cache_mem[0]) +#define FLASH_SECTOR_SIZE_MAX (0x4000) // 16k max due to size of cache buffer +#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (128) // sectors 1,2,3,4: 16k+16k+16k+16k(of 64k)=64k + +#elif defined(STM32F429xx) + +#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k +#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of CCM +#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (224) // sectors 1,2,3,4: 16k+16k+16k+64k=112k + +#elif defined(STM32F439xx) + +#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k +#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of CCM +#define FLASH_MEM_SEG1_START_ADDR (0x08100000) // sector 12 +#define FLASH_MEM_SEG1_NUM_BLOCKS (384) // sectors 12,13,14,15,16,17: 16k+16k+16k+16k+64k+64k(of 128k)=192k +#define FLASH_MEM_SEG2_START_ADDR (0x08140000) // sector 18 +#define FLASH_MEM_SEG2_NUM_BLOCKS (128) // sector 18: 64k(of 128k) + +#elif defined(STM32F746xx) || defined(STM32F767xx) || defined(STM32F769xx) + +// The STM32F746 doesn't really have CCRAM, so we use the 64K DTCM for this. + +#define CACHE_MEM_START_ADDR (0x20000000) // DTCM data RAM, 64k +#define FLASH_SECTOR_SIZE_MAX (0x08000) // 32k max +#define FLASH_MEM_SEG1_START_ADDR (0x08008000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (192) // sectors 1,2,3: 32k+32k+32=96k + +#elif defined(STM32L475xx) || defined(STM32L476xx) + +extern uint8_t _flash_fs_start; +extern uint8_t _flash_fs_end; + +// The STM32L475/6 doesn't have CCRAM, so we use the 32K SRAM2 for this. +#define CACHE_MEM_START_ADDR (0x10000000) // SRAM2 data RAM, 32k +#define FLASH_SECTOR_SIZE_MAX (0x00800) // 2k max +#define FLASH_MEM_SEG1_START_ADDR ((long)&_flash_fs_start) +#define FLASH_MEM_SEG1_NUM_BLOCKS ((&_flash_fs_end - &_flash_fs_start) / 512) + +#else +#error "no internal flash storage support for this MCU" +#endif + +#if !defined(FLASH_MEM_SEG2_START_ADDR) +#define FLASH_MEM_SEG2_START_ADDR (0) // no second segment +#define FLASH_MEM_SEG2_NUM_BLOCKS (0) // no second segment +#endif + +#define FLASH_FLAG_DIRTY (1) +#define FLASH_FLAG_FORCE_WRITE (2) +#define FLASH_FLAG_ERASED (4) +static __IO uint8_t flash_flags = 0; +static uint32_t flash_cache_sector_id; +static uint32_t flash_cache_sector_start; +static uint32_t flash_cache_sector_size; +static uint32_t flash_tick_counter_last_write; + +void flash_bdev_init(void) { + flash_flags = 0; + flash_cache_sector_id = 0; + flash_tick_counter_last_write = 0; +} + +uint32_t flash_bdev_num_blocks(void) { + return FLASH_MEM_SEG1_NUM_BLOCKS + FLASH_MEM_SEG2_NUM_BLOCKS; +} + +void flash_bdev_flush(void) { + if (flash_flags & FLASH_FLAG_DIRTY) { + flash_flags |= FLASH_FLAG_FORCE_WRITE; + while (flash_flags & FLASH_FLAG_DIRTY) { + NVIC->STIR = FLASH_IRQn; + } + } +} + +static uint8_t *flash_cache_get_addr_for_write(uint32_t flash_addr) { + uint32_t flash_sector_start; + uint32_t flash_sector_size; + uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size); + if (flash_sector_size > FLASH_SECTOR_SIZE_MAX) { + flash_sector_size = FLASH_SECTOR_SIZE_MAX; + } + if (flash_cache_sector_id != flash_sector_id) { + flash_bdev_flush(); + memcpy((void*)CACHE_MEM_START_ADDR, (const void*)flash_sector_start, flash_sector_size); + flash_cache_sector_id = flash_sector_id; + flash_cache_sector_start = flash_sector_start; + flash_cache_sector_size = flash_sector_size; + } + flash_flags |= FLASH_FLAG_DIRTY; + led_state(PYB_LED_RED, 1); // indicate a dirty cache with LED on + flash_tick_counter_last_write = HAL_GetTick(); + return (uint8_t*)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start; +} + +static uint8_t *flash_cache_get_addr_for_read(uint32_t flash_addr) { + uint32_t flash_sector_start; + uint32_t flash_sector_size; + uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size); + if (flash_cache_sector_id == flash_sector_id) { + // in cache, copy from there + return (uint8_t*)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start; + } + // not in cache, copy straight from flash + return (uint8_t*)flash_addr; +} + +static uint32_t convert_block_to_flash_addr(uint32_t block) { + if (block < FLASH_MEM_SEG1_NUM_BLOCKS) { + return FLASH_MEM_SEG1_START_ADDR + block * FLASH_BLOCK_SIZE; + } + if (block < FLASH_MEM_SEG1_NUM_BLOCKS + FLASH_MEM_SEG2_NUM_BLOCKS) { + return FLASH_MEM_SEG2_START_ADDR + (block - FLASH_MEM_SEG1_NUM_BLOCKS) * FLASH_BLOCK_SIZE; + } + // can add more flash segments here if needed, following above pattern + + // bad block + return -1; +} + +void flash_bdev_irq_handler(void) { + if (!(flash_flags & FLASH_FLAG_DIRTY)) { + return; + } + + // This code uses interrupts to erase the flash + /* + if (flash_erase_state == 0) { + flash_erase_it(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4); + flash_erase_state = 1; + return; + } + + if (flash_erase_state == 1) { + // wait for erase + // TODO add timeout + #define flash_erase_done() (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) == RESET) + if (!flash_erase_done()) { + return; + } + flash_erase_state = 2; + } + */ + + // This code erases the flash directly, waiting for it to finish + if (!(flash_flags & FLASH_FLAG_ERASED)) { + flash_erase(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4); + flash_flags |= FLASH_FLAG_ERASED; + return; + } + + // If not a forced write, wait at least 5 seconds after last write to flush + // On file close and flash unmount we get a forced write, so we can afford to wait a while + if ((flash_flags & FLASH_FLAG_FORCE_WRITE) || sys_tick_has_passed(flash_tick_counter_last_write, 5000)) { + // sync the cache RAM buffer by writing it to the flash page + flash_write(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4); + // clear the flash flags now that we have a clean cache + flash_flags = 0; + // indicate a clean cache with LED off + led_state(PYB_LED_RED, 0); + } +} + +bool flash_bdev_readblock(uint8_t *dest, uint32_t block) { + // non-MBR block, get data from flash memory, possibly via cache + uint32_t flash_addr = convert_block_to_flash_addr(block); + if (flash_addr == -1) { + // bad block number + return false; + } + uint8_t *src = flash_cache_get_addr_for_read(flash_addr); + memcpy(dest, src, FLASH_BLOCK_SIZE); + return true; +} + +bool flash_bdev_writeblock(const uint8_t *src, uint32_t block) { + // non-MBR block, copy to cache + uint32_t flash_addr = convert_block_to_flash_addr(block); + if (flash_addr == -1) { + // bad block number + return false; + } + uint8_t *dest = flash_cache_get_addr_for_write(flash_addr); + memcpy(dest, src, FLASH_BLOCK_SIZE); + return true; +} + +#endif // !defined(MICROPY_HW_SPIFLASH_SIZE_BITS) diff --git a/ports/stm32/spibdev.c b/ports/stm32/spibdev.c new file mode 100644 index 0000000000..5e5123867d --- /dev/null +++ b/ports/stm32/spibdev.c @@ -0,0 +1,78 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017-2018 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "storage.h" + +#if defined(MICROPY_HW_SPIFLASH_SIZE_BITS) + +#include "drivers/memory/spiflash.h" +#include "genhdr/pins.h" + +STATIC const mp_machine_soft_spi_obj_t spiflash_spi_bus = { + .base = {&mp_machine_soft_spi_type}, + .delay_half = MICROPY_PY_MACHINE_SPI_MIN_DELAY, + .polarity = 0, + .phase = 0, + .sck = &MICROPY_HW_SPIFLASH_SCK, + .mosi = &MICROPY_HW_SPIFLASH_MOSI, + .miso = &MICROPY_HW_SPIFLASH_MISO, +}; + +STATIC const mp_spiflash_t spiflash = { + .cs = &MICROPY_HW_SPIFLASH_CS, + .spi = (mp_obj_base_t*)&spiflash_spi_bus.base, +}; + +void spi_bdev_init(void) { + mp_spiflash_init((mp_spiflash_t*)&spiflash); +} + +bool spi_bdev_readblock(uint8_t *dest, uint32_t block) { + // we must disable USB irqs to prevent MSC contention with SPI flash + uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS); + + mp_spiflash_read((mp_spiflash_t*)&spiflash, + block * FLASH_BLOCK_SIZE, FLASH_BLOCK_SIZE, dest); + + restore_irq_pri(basepri); + + return true; +} + +bool spi_bdev_writeblock(const uint8_t *src, uint32_t block) { + // we must disable USB irqs to prevent MSC contention with SPI flash + uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS); + + int ret = mp_spiflash_write((mp_spiflash_t*)&spiflash, + block * FLASH_BLOCK_SIZE, FLASH_BLOCK_SIZE, src); + + restore_irq_pri(basepri); + + return ret == 0; +} + +#endif // defined(MICROPY_HW_SPIFLASH_SIZE_BITS) diff --git a/ports/stm32/storage.c b/ports/stm32/storage.c index 4b329c2dbb..5eab4c7022 100644 --- a/ports/stm32/storage.c +++ b/ports/stm32/storage.c @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2013-2018 Damien P. George * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,191 +27,51 @@ #include <stdint.h> #include <string.h> -#include "py/obj.h" #include "py/runtime.h" -#include "lib/oofatfs/ff.h" #include "extmod/vfs_fat.h" -#include "systick.h" #include "led.h" -#include "flash.h" #include "storage.h" #include "irq.h" #if defined(MICROPY_HW_SPIFLASH_SIZE_BITS) -#define USE_INTERNAL (0) -#else -#define USE_INTERNAL (1) -#endif - -#if USE_INTERNAL - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) - -#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k -#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of CCM -#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1 -#define FLASH_MEM_SEG1_NUM_BLOCKS (224) // sectors 1,2,3,4: 16k+16k+16k+64k=112k - -// enable this to get an extra 64k of storage (uses the last sector of the flash) -#if 0 -#define FLASH_MEM_SEG2_START_ADDR (0x080e0000) // sector 11 -#define FLASH_MEM_SEG2_NUM_BLOCKS (128) // sector 11: 128k -#endif - -#elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) - -STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k -#define CACHE_MEM_START_ADDR (&flash_cache_mem[0]) -#define FLASH_SECTOR_SIZE_MAX (0x4000) // 16k max due to size of cache buffer -#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1 -#define FLASH_MEM_SEG1_NUM_BLOCKS (128) // sectors 1,2,3,4: 16k+16k+16k+16k(of 64k)=64k - -#elif defined(STM32F429xx) - -#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k -#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of CCM -#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1 -#define FLASH_MEM_SEG1_NUM_BLOCKS (224) // sectors 1,2,3,4: 16k+16k+16k+64k=112k -#elif defined(STM32F439xx) - -#define CACHE_MEM_START_ADDR (0x10000000) // CCM data RAM, 64k -#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of CCM -#define FLASH_MEM_SEG1_START_ADDR (0x08100000) // sector 12 -#define FLASH_MEM_SEG1_NUM_BLOCKS (384) // sectors 12,13,14,15,16,17: 16k+16k+16k+16k+64k+64k(of 128k)=192k -#define FLASH_MEM_SEG2_START_ADDR (0x08140000) // sector 18 -#define FLASH_MEM_SEG2_NUM_BLOCKS (128) // sector 18: 64k(of 128k) - -#elif defined(STM32F746xx) || defined(STM32F767xx) || defined(STM32F769xx) - -// The STM32F746 doesn't really have CCRAM, so we use the 64K DTCM for this. - -#define CACHE_MEM_START_ADDR (0x20000000) // DTCM data RAM, 64k -#define FLASH_SECTOR_SIZE_MAX (0x08000) // 32k max -#define FLASH_MEM_SEG1_START_ADDR (0x08008000) // sector 1 -#define FLASH_MEM_SEG1_NUM_BLOCKS (192) // sectors 1,2,3: 32k+32k+32=96k - -#elif defined(STM32L475xx) || defined(STM32L476xx) - -extern uint8_t _flash_fs_start; -extern uint8_t _flash_fs_end; - -// The STM32L475/6 doesn't have CCRAM, so we use the 32K SRAM2 for this. -#define CACHE_MEM_START_ADDR (0x10000000) // SRAM2 data RAM, 32k -#define FLASH_SECTOR_SIZE_MAX (0x00800) // 2k max -#define FLASH_MEM_SEG1_START_ADDR ((long)&_flash_fs_start) -#define FLASH_MEM_SEG1_NUM_BLOCKS ((&_flash_fs_end - &_flash_fs_start) / 512) +// Use external SPI flash as the storage medium +#define BDEV_NUM_BLOCKS (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) +#define BDEV_INIT spi_bdev_init +#define BDEV_READBLOCK spi_bdev_readblock +#define BDEV_WRITEBLOCK spi_bdev_writeblock #else -#error "no storage support for this MCU" -#endif -#if !defined(FLASH_MEM_SEG2_START_ADDR) -#define FLASH_MEM_SEG2_START_ADDR (0) // no second segment -#define FLASH_MEM_SEG2_NUM_BLOCKS (0) // no second segment +// Use internal flash as the storage medium +#define BDEV_NUM_BLOCKS flash_bdev_num_blocks() +#define BDEV_INIT flash_bdev_init +#define BDEV_IRQ_HANDLER flash_bdev_irq_handler +#define BDEV_FLUSH flash_bdev_flush +#define BDEV_READBLOCK flash_bdev_readblock +#define BDEV_WRITEBLOCK flash_bdev_writeblock + #endif #define FLASH_PART1_START_BLOCK (0x100) -#define FLASH_PART1_NUM_BLOCKS (FLASH_MEM_SEG1_NUM_BLOCKS + FLASH_MEM_SEG2_NUM_BLOCKS) - -#define FLASH_FLAG_DIRTY (1) -#define FLASH_FLAG_FORCE_WRITE (2) -#define FLASH_FLAG_ERASED (4) -static bool flash_is_initialised = false; -static __IO uint8_t flash_flags = 0; -static uint32_t flash_cache_sector_id; -static uint32_t flash_cache_sector_start; -static uint32_t flash_cache_sector_size; -static uint32_t flash_tick_counter_last_write; - -static void flash_cache_flush(void) { - if (flash_flags & FLASH_FLAG_DIRTY) { - flash_flags |= FLASH_FLAG_FORCE_WRITE; - while (flash_flags & FLASH_FLAG_DIRTY) { - NVIC->STIR = FLASH_IRQn; - } - } -} - -static uint8_t *flash_cache_get_addr_for_write(uint32_t flash_addr) { - uint32_t flash_sector_start; - uint32_t flash_sector_size; - uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size); - if (flash_sector_size > FLASH_SECTOR_SIZE_MAX) { - flash_sector_size = FLASH_SECTOR_SIZE_MAX; - } - if (flash_cache_sector_id != flash_sector_id) { - flash_cache_flush(); - memcpy((void*)CACHE_MEM_START_ADDR, (const void*)flash_sector_start, flash_sector_size); - flash_cache_sector_id = flash_sector_id; - flash_cache_sector_start = flash_sector_start; - flash_cache_sector_size = flash_sector_size; - } - flash_flags |= FLASH_FLAG_DIRTY; - led_state(PYB_LED_RED, 1); // indicate a dirty cache with LED on - flash_tick_counter_last_write = HAL_GetTick(); - return (uint8_t*)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start; -} - -static uint8_t *flash_cache_get_addr_for_read(uint32_t flash_addr) { - uint32_t flash_sector_start; - uint32_t flash_sector_size; - uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size); - if (flash_cache_sector_id == flash_sector_id) { - // in cache, copy from there - return (uint8_t*)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start; - } - // not in cache, copy straight from flash - return (uint8_t*)flash_addr; -} - -#else - -#include "drivers/memory/spiflash.h" -#include "genhdr/pins.h" -#define FLASH_PART1_START_BLOCK (0x100) -#define FLASH_PART1_NUM_BLOCKS (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) - -static bool flash_is_initialised = false; - -STATIC const mp_machine_soft_spi_obj_t spiflash_spi_bus = { - .base = {&mp_machine_soft_spi_type}, - .delay_half = MICROPY_PY_MACHINE_SPI_MIN_DELAY, - .polarity = 0, - .phase = 0, - .sck = &MICROPY_HW_SPIFLASH_SCK, - .mosi = &MICROPY_HW_SPIFLASH_MOSI, - .miso = &MICROPY_HW_SPIFLASH_MISO, -}; +static bool storage_is_initialised = false; -STATIC const mp_spiflash_t spiflash = { - .cs = &MICROPY_HW_SPIFLASH_CS, - .spi = (mp_obj_base_t*)&spiflash_spi_bus.base, -}; +void storage_init(void) { + if (!storage_is_initialised) { + storage_is_initialised = true; -#endif + BDEV_INIT(); -void storage_init(void) { - if (!flash_is_initialised) { - #if USE_INTERNAL - flash_flags = 0; - flash_cache_sector_id = 0; - flash_tick_counter_last_write = 0; - #else - mp_spiflash_init((mp_spiflash_t*)&spiflash); + #if defined(BDEV_IRQ_HANDLER) + // Enable the flash IRQ, which is used to also call our storage IRQ handler + // It needs to go at a higher priority than all those components that rely on + // the flash storage (eg higher than USB MSC). + HAL_NVIC_SetPriority(FLASH_IRQn, IRQ_PRI_FLASH, IRQ_SUBPRI_FLASH); + HAL_NVIC_EnableIRQ(FLASH_IRQn); #endif - flash_is_initialised = true; } - - #if USE_INTERNAL - // Enable the flash IRQ, which is used to also call our storage IRQ handler - // It needs to go at a higher priority than all those components that rely on - // the flash storage (eg higher than USB MSC). - HAL_NVIC_SetPriority(FLASH_IRQn, IRQ_PRI_FLASH, IRQ_SUBPRI_FLASH); - HAL_NVIC_EnableIRQ(FLASH_IRQn); - #endif } uint32_t storage_get_block_size(void) { @@ -219,59 +79,18 @@ uint32_t storage_get_block_size(void) { } uint32_t storage_get_block_count(void) { - return FLASH_PART1_START_BLOCK + FLASH_PART1_NUM_BLOCKS; + return FLASH_PART1_START_BLOCK + BDEV_NUM_BLOCKS; } void storage_irq_handler(void) { - #if USE_INTERNAL - - if (!(flash_flags & FLASH_FLAG_DIRTY)) { - return; - } - - // This code uses interrupts to erase the flash - /* - if (flash_erase_state == 0) { - flash_erase_it(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4); - flash_erase_state = 1; - return; - } - - if (flash_erase_state == 1) { - // wait for erase - // TODO add timeout - #define flash_erase_done() (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) == RESET) - if (!flash_erase_done()) { - return; - } - flash_erase_state = 2; - } - */ - - // This code erases the flash directly, waiting for it to finish - if (!(flash_flags & FLASH_FLAG_ERASED)) { - flash_erase(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4); - flash_flags |= FLASH_FLAG_ERASED; - return; - } - - // If not a forced write, wait at least 5 seconds after last write to flush - // On file close and flash unmount we get a forced write, so we can afford to wait a while - if ((flash_flags & FLASH_FLAG_FORCE_WRITE) || sys_tick_has_passed(flash_tick_counter_last_write, 5000)) { - // sync the cache RAM buffer by writing it to the flash page - flash_write(flash_cache_sector_start, (const uint32_t*)CACHE_MEM_START_ADDR, flash_cache_sector_size / 4); - // clear the flash flags now that we have a clean cache - flash_flags = 0; - // indicate a clean cache with LED off - led_state(PYB_LED_RED, 0); - } - + #if defined(BDEV_IRQ_HANDLER) + BDEV_IRQ_HANDLER(); #endif } void storage_flush(void) { - #if USE_INTERNAL - flash_cache_flush(); + #if defined(BDEV_FLUSH) + BDEV_FLUSH(); #endif } @@ -311,25 +130,6 @@ static void build_partition(uint8_t *buf, int boot, int type, uint32_t start_blo buf[15] = num_blocks >> 24; } -#if USE_INTERNAL - -static uint32_t convert_block_to_flash_addr(uint32_t block) { - if (FLASH_PART1_START_BLOCK <= block && block < FLASH_PART1_START_BLOCK + FLASH_PART1_NUM_BLOCKS) { - // a block in partition 1 - block -= FLASH_PART1_START_BLOCK; - if (block < FLASH_MEM_SEG1_NUM_BLOCKS) { - return FLASH_MEM_SEG1_START_ADDR + block * FLASH_BLOCK_SIZE; - } else if (block < FLASH_MEM_SEG1_NUM_BLOCKS + FLASH_MEM_SEG2_NUM_BLOCKS) { - return FLASH_MEM_SEG2_START_ADDR + (block - FLASH_MEM_SEG1_NUM_BLOCKS) * FLASH_BLOCK_SIZE; - } - // can add more flash segments here if needed, following above pattern - } - // bad block - return -1; -} - -#endif - bool storage_read_block(uint8_t *dest, uint32_t block) { //printf("RD %u\n", block); if (block == 0) { @@ -339,7 +139,7 @@ bool storage_read_block(uint8_t *dest, uint32_t block) { dest[i] = 0; } - build_partition(dest + 446, 0, 0x01 /* FAT12 */, FLASH_PART1_START_BLOCK, FLASH_PART1_NUM_BLOCKS); + build_partition(dest + 446, 0, 0x01 /* FAT12 */, FLASH_PART1_START_BLOCK, BDEV_NUM_BLOCKS); build_partition(dest + 462, 0, 0, 0, 0); build_partition(dest + 478, 0, 0, 0, 0); build_partition(dest + 494, 0, 0, 0, 0); @@ -349,39 +149,10 @@ bool storage_read_block(uint8_t *dest, uint32_t block) { return true; + } else if (FLASH_PART1_START_BLOCK <= block && block < FLASH_PART1_START_BLOCK + BDEV_NUM_BLOCKS) { + return BDEV_READBLOCK(dest, block - FLASH_PART1_START_BLOCK); } else { - #if USE_INTERNAL - - // non-MBR block, get data from flash memory, possibly via cache - uint32_t flash_addr = convert_block_to_flash_addr(block); - if (flash_addr == -1) { - // bad block number - return false; - } - uint8_t *src = flash_cache_get_addr_for_read(flash_addr); - memcpy(dest, src, FLASH_BLOCK_SIZE); - return true; - - #else - - // non-MBR block, get data from SPI flash - - if (block < FLASH_PART1_START_BLOCK || block >= FLASH_PART1_START_BLOCK + FLASH_PART1_NUM_BLOCKS) { - // bad block number - return false; - } - - // we must disable USB irqs to prevent MSC contention with SPI flash - uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS); - - mp_spiflash_read((mp_spiflash_t*)&spiflash, - (block - FLASH_PART1_START_BLOCK) * FLASH_BLOCK_SIZE, FLASH_BLOCK_SIZE, dest); - - restore_irq_pri(basepri); - - return true; - - #endif + return false; } } @@ -390,40 +161,10 @@ bool storage_write_block(const uint8_t *src, uint32_t block) { if (block == 0) { // can't write MBR, but pretend we did return true; - + } else if (FLASH_PART1_START_BLOCK <= block && block < FLASH_PART1_START_BLOCK + BDEV_NUM_BLOCKS) { + return BDEV_WRITEBLOCK(src, block - FLASH_PART1_START_BLOCK); } else { - #if USE_INTERNAL - - // non-MBR block, copy to cache - uint32_t flash_addr = convert_block_to_flash_addr(block); - if (flash_addr == -1) { - // bad block number - return false; - } - uint8_t *dest = flash_cache_get_addr_for_write(flash_addr); - memcpy(dest, src, FLASH_BLOCK_SIZE); - return true; - - #else - - // non-MBR block, write to SPI flash - - if (block < FLASH_PART1_START_BLOCK || block >= FLASH_PART1_START_BLOCK + FLASH_PART1_NUM_BLOCKS) { - // bad block number - return false; - } - - // we must disable USB irqs to prevent MSC contention with SPI flash - uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS); - - int ret = mp_spiflash_write((mp_spiflash_t*)&spiflash, - (block - FLASH_PART1_START_BLOCK) * FLASH_BLOCK_SIZE, FLASH_BLOCK_SIZE, src); - - restore_irq_pri(basepri); - - return ret == 0; - - #endif + return false; } } diff --git a/ports/stm32/storage.h b/ports/stm32/storage.h index 291e09a9ae..5533a2a930 100644 --- a/ports/stm32/storage.h +++ b/ports/stm32/storage.h @@ -43,6 +43,17 @@ bool storage_write_block(const uint8_t *src, uint32_t block); mp_uint_t storage_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blocks); mp_uint_t storage_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks); +uint32_t flash_bdev_num_blocks(void); +void flash_bdev_init(void); +void flash_bdev_irq_handler(void); +void flash_bdev_flush(void); +bool flash_bdev_readblock(uint8_t *dest, uint32_t block); +bool flash_bdev_writeblock(const uint8_t *src, uint32_t block); + +void spi_bdev_init(void); +bool spi_bdev_readblock(uint8_t *dest, uint32_t block); +bool spi_bdev_writeblock(const uint8_t *src, uint32_t block); + extern const struct _mp_obj_type_t pyb_flash_type; struct _fs_user_mount_t; |