diff options
| author | Damien George <damien.p.george@gmail.com> | 2014-10-26 13:54:31 +0000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2014-10-26 13:54:31 +0000 |
| commit | 480a7ce58f6e5dc6179373f1f8b69d6a5434b2d4 (patch) | |
| tree | 613e678dfd9fbf244332b0a2d3bd22b196974163 /tests/pyb/spi.py | |
| parent | de3c806965f907981d5cb5d49fc139845cd94aba (diff) | |
| download | micropython-480a7ce58f6e5dc6179373f1f8b69d6a5434b2d4.tar.gz micropython-480a7ce58f6e5dc6179373f1f8b69d6a5434b2d4.zip | |
stmhal: Change SPI phase spec to 0,1 to match standard conventions.
Was 1 or 2, now 0 or 1 (respectively). 0 means sample MISO on first
edge, 1 means sample on second edge.
Addresses issue #936.
Diffstat (limited to 'tests/pyb/spi.py')
| -rw-r--r-- | tests/pyb/spi.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/pyb/spi.py b/tests/pyb/spi.py index 90dfb441a3..24a7a85a54 100644 --- a/tests/pyb/spi.py +++ b/tests/pyb/spi.py @@ -5,10 +5,10 @@ print(spi) spi = SPI(1, SPI.MASTER) spi = SPI(1, SPI.MASTER, baudrate=500000) -spi = SPI(1, SPI.MASTER, 500000, polarity=1, phase=1, bits=8, firstbit=SPI.MSB, ti=False, crc=None) +spi = SPI(1, SPI.MASTER, 500000, polarity=1, phase=0, bits=8, firstbit=SPI.MSB, ti=False, crc=None) print(spi) -spi.init(SPI.SLAVE) +spi.init(SPI.SLAVE, phase=1) print(spi) spi.init(SPI.MASTER) |