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author | Damien George <damien.p.george@gmail.com> | 2014-08-25 17:36:14 +0100 |
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committer | Damien George <damien.p.george@gmail.com> | 2014-08-25 17:38:55 +0100 |
commit | 29c92a407c8fa04a205f10c4efdb5696e0cf0b58 (patch) | |
tree | 5cb842957202c012732af682f7982031d45acd24 /stmhal/systick.c | |
parent | 2bf044442eae7dbdaff91051d2c135b4aa51f1b2 (diff) | |
download | micropython-29c92a407c8fa04a205f10c4efdb5696e0cf0b58.tar.gz micropython-29c92a407c8fa04a205f10c4efdb5696e0cf0b58.zip |
stmhal: Use MP_OBJ_NEW_SMALL_INT directly in pyb.micros/millis.
Also some whitespace cleanup.
Diffstat (limited to 'stmhal/systick.c')
-rw-r--r-- | stmhal/systick.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/stmhal/systick.c b/stmhal/systick.c index 660b777fc0..b2381d08eb 100644 --- a/stmhal/systick.c +++ b/stmhal/systick.c @@ -51,29 +51,29 @@ void sys_tick_wait_at_least(uint32_t start_tick, uint32_t delay_ms) { // // We assume that HAL_GetTickis returns milliseconds. uint32_t sys_tick_get_microseconds(void) { - mp_int_t enabled = disable_irq(); + mp_uint_t irq_state = disable_irq(); uint32_t counter = SysTick->VAL; uint32_t milliseconds = HAL_GetTick(); uint32_t status = SysTick->CTRL; - enable_irq(enabled); + enable_irq(irq_state); - // It's still possible for the countflag bit to get set if the counter was - // reloaded between reading VAL and reading CTRL. With interrupts disabled - // it definitely takes less than 50 HCLK cycles between reading VAL and - // reading CTRL, so the test (counter > 50) is to cover the case where VAL - // is +ve and very close to zero, and the COUNTFLAG bit is also set. - if ((status & SysTick_CTRL_COUNTFLAG_Msk) && counter > 50) { - // This means that the HW reloaded VAL between the time we read VAL and the - // time we read CTRL, which implies that there is an interrupt pending - // to increment the tick counter. - milliseconds++; - } - uint32_t load = SysTick->LOAD; - counter = load - counter; // Convert from decrementing to incrementing + // It's still possible for the countflag bit to get set if the counter was + // reloaded between reading VAL and reading CTRL. With interrupts disabled + // it definitely takes less than 50 HCLK cycles between reading VAL and + // reading CTRL, so the test (counter > 50) is to cover the case where VAL + // is +ve and very close to zero, and the COUNTFLAG bit is also set. + if ((status & SysTick_CTRL_COUNTFLAG_Msk) && counter > 50) { + // This means that the HW reloaded VAL between the time we read VAL and the + // time we read CTRL, which implies that there is an interrupt pending + // to increment the tick counter. + milliseconds++; + } + uint32_t load = SysTick->LOAD; + counter = load - counter; // Convert from decrementing to incrementing - // ((load + 1) / 1000) is the number of counts per microsecond. - // - // counter / ((load + 1) / 1000) scales from the systick clock to microseconds - // and is the same thing as (counter * 1000) / (load + 1) - return milliseconds * 1000 + (counter * 1000) / (load + 1); + // ((load + 1) / 1000) is the number of counts per microsecond. + // + // counter / ((load + 1) / 1000) scales from the systick clock to microseconds + // and is the same thing as (counter * 1000) / (load + 1) + return milliseconds * 1000 + (counter * 1000) / (load + 1); } |