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| author | mux <freelancer.c@gmail.com> | 2014-01-23 18:27:29 +0200 |
|---|---|---|
| committer | mux <freelancer.c@gmail.com> | 2014-01-23 18:27:29 +0200 |
| commit | 1d1e4e1bd5e95d609460e022ea395cd676b5e009 (patch) | |
| tree | 34924f3904b03e02916898bd3cd6266265de6cb8 /stm/lib/usb_dcd_int.c | |
| parent | 638179fb9cea822c30a84f35dd7685660e6d6c41 (diff) | |
| download | micropython-1d1e4e1bd5e95d609460e022ea395cd676b5e009.tar.gz micropython-1d1e4e1bd5e95d609460e022ea395cd676b5e009.zip | |
Fix USB CORE PCGCCTL Wrong Address
* Fix PCGCCTL bug using address instead of value.
* Fix issue #211
Diffstat (limited to 'stm/lib/usb_dcd_int.c')
| -rw-r--r-- | stm/lib/usb_dcd_int.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/stm/lib/usb_dcd_int.c b/stm/lib/usb_dcd_int.c index 7089f34978..4dd9ce8396 100644 --- a/stm/lib/usb_dcd_int.c +++ b/stm/lib/usb_dcd_int.c @@ -352,7 +352,7 @@ static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev) if(pdev->cfg.low_power)
{
/* un-gate USB Core clock */
- power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); // dpgeorge: taking the address here might be wrong...
+ power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL);
power.b.gatehclk = 0;
power.b.stoppclk = 0;
USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
|