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| author | iabdalkader <i.abdalkader@gmail.com> | 2021-09-30 09:13:15 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2021-10-15 17:59:31 +1100 |
| commit | eea6cd85b37351ceda1b4c80a804912605977997 (patch) | |
| tree | 9ab18763f39f01ff0b9cbb3016fc9563576d7df6 /py/obj.c | |
| parent | 4c9e17e0a16266523e5d89640f756a1a0ad2d8e3 (diff) | |
| download | micropython-eea6cd85b37351ceda1b4c80a804912605977997.tar.gz micropython-eea6cd85b37351ceda1b4c80a804912605977997.zip | |
stm32/sdram: Enforce gcc opt, and use volatile and DSB in sdram_test.
Ensures consistent behaviour and resolves the D-Cache bug (the "exhaustive"
argument being lost due to cache being turned off) when O0 is used.
The changes in this commit are:
- Change -O0 to -Os because "gcc is considered broken at -O0" according to
https://github.com/ARM-software/CMSIS_5/issues/620#issuecomment-550235656
- Use volatile for mem_base so the compiler doesn't optimise away reads or
writes to the SDRAM, which is being tested.
- Use DSB to prevent any other compiler optimisations that would change the
testing logic.
- Use alternating pattern/antipattern in exhaustive test to catch more
hardware/configuration errors.
Implementation adapted by @andrewleech, taken directly from investigation
by @iabdalkader and @dpgeorge.
See #7841 and #7869 for further discussion.
Diffstat (limited to 'py/obj.c')
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