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authorPaul Sokolovsky <pfalcon@users.sourceforge.net>2015-10-24 02:26:10 +0300
committerPaul Sokolovsky <pfalcon@users.sourceforge.net>2015-10-24 15:46:53 +0300
commit0dbd928ceefed09d65276211c70d0137b4734011 (patch)
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Makefiles: Remove duplicate object files when linking.
Scenario: module1 depends on some common file from lib/, so specifies it in its SRC_MOD, and the same situation with module2, then common file from lib/ eventually ends up listed twice in $(OBJ), which leads to link errors. Make is equipped to deal with such situation easily, quoting the manual: "The value of $^ omits duplicate prerequisites, while $+ retains them and preserves their order." So, just use $^ consistently in all link targets.
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