py/emitnative: Refactor Viper register-indexed load/stores.

This commit cleans up the Viper code generation blocks for
register-indexed load and store operations.

An attempt is made to simplify the code in the common code generator
code block, by moving architecture-specific code to the appropriate
native generation backends whenever possible.  This should make that
specific bit of code in the Viper generator clearer and easier to
maintain in the long term.

To achieve this, six generic assembler meta-opcodes have been
introduced, named `ASM_{LOAD,STORE}{8,16,32}_REG_REG_REG`.  A
platform-independent implementation for those operations is provided, so
backends that cannot emit a shorter sequence for the requested operation
or are fine with the platform-independent implementation can just not
provide said meta-opcodes.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

0 files changed, 0 insertions, 0 deletions