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authorAlessandro Gatti <a.gatti@frob.it>2025-05-07 22:41:33 +0200
committerAlessandro Gatti <a.gatti@frob.it>2025-05-21 01:50:12 +0200
commitb6d269ee32026c7380fdb6ebcbc7e50e84239c12 (patch)
treea7fc35fb0e2000e59142299c4464fc8f09b821f9 /docs/esp32/tutorial
parent04c6b99cb941cdc00822f17fe530a63639359019 (diff)
downloadmicropython-b6d269ee32026c7380fdb6ebcbc7e50e84239c12.tar.gz
micropython-b6d269ee32026c7380fdb6ebcbc7e50e84239c12.zip
py/emitnative: Refactor Viper register-indexed load/stores.
This commit cleans up the Viper code generation blocks for register-indexed load and store operations. An attempt is made to simplify the code in the common code generator code block, by moving architecture-specific code to the appropriate native generation backends whenever possible. This should make that specific bit of code in the Viper generator clearer and easier to maintain in the long term. To achieve this, six generic assembler meta-opcodes have been introduced, named `ASM_{LOAD,STORE}{8,16,32}_REG_REG_REG`. A platform-independent implementation for those operations is provided, so backends that cannot emit a shorter sequence for the requested operation or are fine with the platform-independent implementation can just not provide said meta-opcodes. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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