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| author | Damien George <damien.p.george@gmail.com> | 2014-05-31 18:13:28 +0100 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2014-05-31 18:13:28 +0100 |
| commit | 6e18835b94d488d39c4a0c00f95e810bb8c905aa (patch) | |
| tree | fa4fb7b928f7e00642e097f8e4218744a00cb097 | |
| parent | a053e37b2cd453db35ca28e5292e24ec898e585f (diff) | |
| parent | b5fb9b22e254c971fe79a91f8c225a6bf4abb93b (diff) | |
| download | micropython-6e18835b94d488d39c4a0c00f95e810bb8c905aa.tar.gz micropython-6e18835b94d488d39c4a0c00f95e810bb8c905aa.zip | |
Merge pull request #643 from dhylands/fix-af-csv
Add a comma to make the .csv look proper in github
| -rw-r--r-- | stmhal/boards/stm32f4xx-af.csv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/stmhal/boards/stm32f4xx-af.csv b/stmhal/boards/stm32f4xx-af.csv index 5746ac8cc9..466be06002 100644 --- a/stmhal/boards/stm32f4xx-af.csv +++ b/stmhal/boards/stm32f4xx-af.csv @@ -1,4 +1,4 @@ -Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15 +Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15, ,,SYS,TIM1/2,TIM3/4/5,TIM8/9/10/11,I2C1/2/3,SPI1/SPI2/I2S2/I2S2ext,SPI3/I2Sext/I2S3,USART1/2/3/I2S3ext,UART4/5/USART6,CAN1/CAN2/TIM12/13/14,OTG_FS/OTG_HS,ETH,FSMC/SDIO/OTG_FS,DCMI,,,ADC PortA,PA0,,TIM2_CH1_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,ETH_MII_CRS,,,,EVENTOUT,ADC123_IN0 PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,,,ETH_MII_RX_CLK/ETH_RMII__REF_CLK,,,,EVENTOUT,ADC123_IN1 |