diff options
Diffstat (limited to 'stm/system_stm32f4xx.c')
| -rw-r--r-- | stm/system_stm32f4xx.c | 480 |
1 files changed, 424 insertions, 56 deletions
diff --git a/stm/system_stm32f4xx.c b/stm/system_stm32f4xx.c index 7d13dbe8e9..8568a9b4f1 100644 --- a/stm/system_stm32f4xx.c +++ b/stm/system_stm32f4xx.c @@ -1,13 +1,11 @@ /**
******************************************************************************
- * @file system_stm32f4xx.c
+ * @file Project/STM32F4xx_StdPeriph_Templates/system_stm32f4xx.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
+ * @version V1.3.0
+ * @date 13-November-2013
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- * This file contains the system clock configuration for STM32F4xx devices,
- * and is generated by the clock configuration tool
- * stm32f4xx_Clock_Configuration_V1.1.0.xls
+ * This file contains the system clock configuration for STM32F4xx devices.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
@@ -42,7 +40,7 @@ * 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
- * Supported STM32F40xx/41xx/427x/437x devices
+ * Supported STM32F40xxx/41xxx devices
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
@@ -88,6 +86,100 @@ * SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
+ *=============================================================================
+ * Supported STM32F42xxx/43xxx devices
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 180000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 180000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 4
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 25000000
+ *-----------------------------------------------------------------------------
+ * PLL_M | 25
+ *-----------------------------------------------------------------------------
+ * PLL_N | 360
+ *-----------------------------------------------------------------------------
+ * PLL_P | 2
+ *-----------------------------------------------------------------------------
+ * PLL_Q | 7
+ *-----------------------------------------------------------------------------
+ * PLLI2S_N | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_R | NA
+ *-----------------------------------------------------------------------------
+ * I2S input clock | NA
+ *-----------------------------------------------------------------------------
+ * VDD(V) | 3.3
+ *-----------------------------------------------------------------------------
+ * Main regulator output voltage | Scale1 mode
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 5
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ * Instruction cache | ON
+ *-----------------------------------------------------------------------------
+ * Data cache | ON
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB OTG FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ *=============================================================================
+ * Supported STM32F401xx devices
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 84000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 84000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 25000000
+ *-----------------------------------------------------------------------------
+ * PLL_M | 25
+ *-----------------------------------------------------------------------------
+ * PLL_N | 336
+ *-----------------------------------------------------------------------------
+ * PLL_P | 4
+ *-----------------------------------------------------------------------------
+ * PLL_Q | 7
+ *-----------------------------------------------------------------------------
+ * PLLI2S_N | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_R | NA
+ *-----------------------------------------------------------------------------
+ * I2S input clock | NA
+ *-----------------------------------------------------------------------------
+ * VDD(V) | 3.3
+ *-----------------------------------------------------------------------------
+ * Main regulator output voltage | Scale1 mode
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 2
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ * Instruction cache | ON
+ *-----------------------------------------------------------------------------
+ * Data cache | ON
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB OTG FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
******************************************************************************
* @attention
*
@@ -139,9 +231,16 @@ */
/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM mounted
- on STM324xG_EVAL/STM324x7I_EVAL boards as data memory */
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+ on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */
+
+#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427_437x || STM32F429_439xx */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@@ -153,13 +252,26 @@ /************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 8
+/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
+#define PLL_Q 7
+
+#if defined (STM32F40_41xxx)
#define PLL_N 336
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P 2
+#endif /* STM32F40_41xxx */
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#define PLL_N 360
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
+#endif /* STM32F427_437x || STM32F429_439xx */
-/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
-#define PLL_Q 7
+#if defined (STM32F401xx)
+#define PLL_N 336
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P 4
+#endif /* STM32F401xx */
/******************************************************************************/
@@ -179,7 +291,17 @@ * @{
*/
+#if defined (STM32F40_41xxx)
uint32_t SystemCoreClock = 168000000;
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+ uint32_t SystemCoreClock = 180000000;
+#endif /* STM32F427_437x || STM32F429_439xx */
+
+#if defined (STM32F401xx)
+ uint32_t SystemCoreClock = 84000000;
+#endif /* STM32F401xx */
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
@@ -192,9 +314,10 @@ */
static void SetSysClock(void);
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @}
@@ -236,9 +359,9 @@ void SystemInit(void) /* Disable all interrupts */
RCC->CIR = 0x00000000;
-#ifdef DATA_IN_ExtSRAM
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM */
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
@@ -372,19 +495,29 @@ static void SetSysClock(void) if (HSEStatus == (uint32_t)0x01)
{
- /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
+ /* Select regulator voltage output Scale 1 mode */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
+
+#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
+#if defined (STM32F401xx)
+ /* PCLK2 = HCLK / 2*/
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK / 4*/
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
+#endif /* STM32F401xx */
+
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
@@ -397,8 +530,29 @@ static void SetSysClock(void) {
}
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+ /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
+ PWR->CR |= PWR_CR_ODEN;
+ while((PWR->CSR & PWR_CSR_ODRDY) == 0)
+ {
+ }
+ PWR->CR |= PWR_CR_ODSWEN;
+ while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
+ {
+ }
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+#endif /* STM32F427_437x || STM32F429_439xx */
+
+#if defined (STM32F40_41xxx)
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F401xx)
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
- FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
+#endif /* STM32F401xx */
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
@@ -435,31 +589,28 @@ void SystemInit_ExtMemCtl(void) {
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
- +-------------------+--------------------+------------------+------------------+
- + SRAM pins assignment +
- +-------------------+--------------------+------------------+------------------+
- | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 |
- | PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 |
- | PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+
- | PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 |
- +-------------------| PE12 <-> FSMC_D9 |
- | PE13 <-> FSMC_D10 |
- | PE14 <-> FSMC_D11 |
- | PE15 <-> FSMC_D12 |
- +--------------------+
+ +-------------------+--------------------+------------------+--------------+
+ + SRAM pins assignment +
+ +-------------------+--------------------+------------------+--------------+
+ | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
+ | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
+ | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
+ | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
+ | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
+ | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
+ | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
+ | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
+ | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
+ | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
+ | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
+ | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
+ | | PE15 <-> FMC_D12 |
+ +------------------+------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
- /* Connect PDx pins to FSMC Alternate function */
+ /* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcccccccc;
/* Configure PDx pins in Alternate function mode */
@@ -471,7 +622,7 @@ void SystemInit_ExtMemCtl(void) /* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
- /* Connect PEx pins to FSMC Alternate function */
+ /* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xcccccccc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
@@ -483,7 +634,7 @@ void SystemInit_ExtMemCtl(void) /* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
- /* Connect PFx pins to FSMC Alternate function */
+ /* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
@@ -495,7 +646,7 @@ void SystemInit_ExtMemCtl(void) /* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
- /* Connect PGx pins to FSMC Alternate function */
+ /* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
@@ -507,24 +658,34 @@ void SystemInit_ExtMemCtl(void) /* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
-/*-- FSMC Configuration ------------------------------------------------------*/
- /* Enable the FSMC interface clock */
+/*-- FMC Configuration ------------------------------------------------------*/
+ /* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427_437xx || STM32F429_439xx */
+#if defined (STM32F40_41xxx)
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F40_41xxx */
+
/*
Bank1_SRAM2 is configured as follow:
-
- p.FSMC_AddressSetupTime = 1;
- p.FSMC_AddressHoldTime = 0;
- p.FSMC_DataSetupTime = 2;
- p.FSMC_BusTurnAroundDuration = 0;
- p.FSMC_CLKDivision = 0;
- p.FSMC_DataLatency = 0;
- p.FSMC_AccessMode = FSMC_AccessMode_A;
+ In case of FSMC configuration
+ NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
+ NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
+ NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
+ NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
+ NORSRAMTimingStructure.FSMC_CLKDivision = 0;
+ NORSRAMTimingStructure.FSMC_DataLatency = 0;
+ NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
@@ -539,11 +700,219 @@ void SystemInit_ExtMemCtl(void) FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
- FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
+
+ In case of FMC configuration
+ NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
+ NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
+ NORSRAMTimingStructure.FMC_DataSetupTime = 2;
+ NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
+ NORSRAMTimingStructure.FMC_CLKDivision = 0;
+ NORSRAMTimingStructure.FMC_DataLatency = 0;
+ NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
+
+ FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
+ FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
+ FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
+ FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
+ FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
+ FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
+ FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
+ FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
+ FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
+ FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
+ FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
+ FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
+ FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
+ FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
+ FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
+ FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
*/
+
}
#endif /* DATA_IN_ExtSRAM */
+
+#ifdef DATA_IN_ExtSDRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external SDRAM mounted on STM324x9I_EVAL board
+ * This SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register uint32_t index;
+
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ clock */
+ RCC->AHB1ENR |= 0x000001FC;
+
+ /* Connect PCx pins to FMC Alternate function */
+ GPIOC->AFR[0] = 0x0000000c;
+ GPIOC->AFR[1] = 0x00007700;
+ /* Configure PCx pins in Alternate function mode */
+ GPIOC->MODER = 0x00a00002;
+ /* Configure PCx pins speed to 50 MHz */
+ GPIOC->OSPEEDR = 0x00a00002;
+ /* Configure PCx pins Output type to push-pull */
+ GPIOC->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PCx pins */
+ GPIOC->PUPDR = 0x00500000;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xA02A000A;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOD->OSPEEDR = 0xA02A000A;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 50 MHz */
+ GPIOE->OSPEEDR = 0xAAAA800A;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xcccccccc;
+ GPIOF->AFR[1] = 0xcccccccc;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xcccccccc;
+ GPIOG->AFR[1] = 0xcccccccc;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xaaaaaaaa;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xaaaaaaaa;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+ /* Configure and enable SDRAM bank1 */
+ FMC_Bank5_6->SDCR[0] = 0x000039D0;
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) & (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) & (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+ FMC_Bank5_6->SDCMR = 0x00000073;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) & (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+ FMC_Bank5_6->SDCMR = 0x00046014;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) & (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+/*
+ Bank1_SDRAM is configured as follow:
+
+ FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
+ FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
+ FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
+ FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
+ FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
+ FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
+ FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
+
+ FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
+ FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
+ FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
+ FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
+ FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
+ FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
+ FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
+ FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
+ FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
+ FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
+ FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
+*/
+
+}
+#endif /* DATA_IN_ExtSDRAM */
/**
@@ -558,4 +927,3 @@ void SystemInit_ExtMemCtl(void) * @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
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