summaryrefslogtreecommitdiffstatshomepage
path: root/stm/lib/stm32f4xx_flash.c
diff options
context:
space:
mode:
Diffstat (limited to 'stm/lib/stm32f4xx_flash.c')
-rw-r--r--stm/lib/stm32f4xx_flash.c485
1 files changed, 444 insertions, 41 deletions
diff --git a/stm/lib/stm32f4xx_flash.c b/stm/lib/stm32f4xx_flash.c
index ba16c3f579..f3551b116e 100644
--- a/stm/lib/stm32f4xx_flash.c
+++ b/stm/lib/stm32f4xx_flash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 11-January-2013
+ * @version V1.3.0
+ * @date 08-November-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* + FLASH Interface configuration
@@ -70,7 +70,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_flash.h"
-#include "stm32f4xx_conf.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -108,6 +107,8 @@
To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device.
+ [..]
+ For STM32F405xx/07xx and STM32F415xx/17xx devices
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
@@ -124,11 +125,57 @@
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
|---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
+ |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
+ +---------------|----------------|----------------|-----------------|-----------------+
+
+ [..]
+ For STM32F42xxx/43xxx devices
+ +-------------------------------------------------------------------------------------+
+ | Latency | HCLK clock frequency (MHz) |
+ | |---------------------------------------------------------------------|
+ | | voltage range | voltage range | voltage range | voltage range |
+ | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
+ +-------------------------------------------------------------------------------------+
+
+ [..]
+ For STM32F401x devices
+ +-------------------------------------------------------------------------------------+
+ | Latency | HCLK clock frequency (MHz) |
+ | |---------------------------------------------------------------------|
+ | | voltage range | voltage range | voltage range | voltage range |
+ | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
+-------------------------------------------------------------------------------------+
[..]
@@ -140,16 +187,20 @@
|---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
|PSIZE[1:0] | 10 | 01 | 00 | 11 |
+-------------------------------------------------------------------------------------------------------------------+
- -@- When VOS bit (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
- You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
- -@- On STM32F40xx/41xx devices:
- (++) when VOS = '0', the maximum value of fHCLK = 144MHz.
- (++) when VOS = '1', the maximum value of fHCLK = 168MHz.
+
+ -@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
+ (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz.
+ (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz.
[..]
- On STM32F427x/437x devices:
- (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
- (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
- (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
+ On STM32F42xxx/43xxx devices:
+ (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
+ (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
+ (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON.
+ [..]
+ On STM32F401x devices:
+ (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
+ (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
+ For more details please refer product DataSheet
You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
(+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
@@ -176,9 +227,22 @@
* @arg FLASH_Latency_4: FLASH Four Latency cycles
* @arg FLASH_Latency_5: FLASH Five Latency cycles
* @arg FLASH_Latency_6: FLASH Six Latency cycles
- * @arg FLASH_Latency_7: FLASH Seven Latency cycles
- * For STM32F40xx/41xx and STM32F427x/437x devices this parameter can be
- * a value between FLASH_Latency_0 and FLASH_Latency_7.
+ * @arg FLASH_Latency_7: FLASH Seven Latency cycles
+ * @arg FLASH_Latency_8: FLASH Eight Latency cycles
+ * @arg FLASH_Latency_9: FLASH Nine Latency cycles
+ * @arg FLASH_Latency_10: FLASH Teen Latency cycles
+ * @arg FLASH_Latency_11: FLASH Eleven Latency cycles
+ * @arg FLASH_Latency_12: FLASH Twelve Latency cycles
+ * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles
+ * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
+ * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
+ *
+ * @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx devices this parameter
+ * can be a value between FLASH_Latency_0 and FLASH_Latency_7.
+ *
+ * @note For STM32F42xxx/43xxx devices this parameter can be a value between
+ * FLASH_Latency_0 and FLASH_Latency_15.
+ *
* @retval None
*/
void FLASH_SetLatency(uint32_t FLASH_Latency)
@@ -296,7 +360,10 @@ void FLASH_DataCacheReset(void)
(+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
(+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
(+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
- (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
+ (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
+ The following functions can be used only for STM32F42xxx/43xxx devices.
+ (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
+ (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
[..]
Any operation of erase or program should follow these steps:
(#) Call the FLASH_Unlock() function to enable the FLASH control register access
@@ -343,10 +410,15 @@ void FLASH_Lock(void)
* the erase operation is performed before the program one.
*
* @param FLASH_Sector: The Sector number to be erased.
- * For STM32F40xx/41xx devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_11.
- * For STM32F427x/437x devices this parameter can be a value between
- * FLASH_Sector_0 and FLASH_Sector_23.
+ *
+ * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can
+ * be a value between FLASH_Sector_0 and FLASH_Sector_11.
+ *
+ * For STM32F42xxx/43xxx devices this parameter can be a value between
+ * FLASH_Sector_0 and FLASH_Sector_23.
+ *
+ * For STM32F401xx devices this parameter can be a value between
+ * FLASH_Sector_0 and FLASH_Sector_5.
*
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
@@ -458,7 +530,7 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all sectors */
-#if defined (STM32F427X)
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
@@ -469,9 +541,9 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
-#endif /* STM32F427X */
+#endif /* STM32F427_437xx || STM32F429_439xx */
-#ifdef STM32F40XX
+#if defined (STM32F40_41xxx) || defined (STM32F401xx)
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
FLASH->CR |= FLASH_CR_MER;
@@ -482,7 +554,140 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= (~FLASH_CR_MER);
-#endif /* STM32F40XX */
+#endif /* STM32F40_41xxx || STM32F401xx */
+
+ }
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH Sectors in Bank 1.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param VoltageRange: The device voltage range which defines the erase parallelism.
+ * This parameter can be one of the following values:
+ * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
+ * the operation will be done by byte (8-bit)
+ * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
+ * the operation will be done by half word (16-bit)
+ * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
+ * the operation will be done by word (32-bit)
+ * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * the operation will be done by double word (64-bit)
+ *
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+ * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
+{
+ uint32_t tmp_psize = 0x0;
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation();
+ assert_param(IS_VOLTAGERANGE(VoltageRange));
+
+ if(VoltageRange == VoltageRange_1)
+ {
+ tmp_psize = FLASH_PSIZE_BYTE;
+ }
+ else if(VoltageRange == VoltageRange_2)
+ {
+ tmp_psize = FLASH_PSIZE_HALF_WORD;
+ }
+ else if(VoltageRange == VoltageRange_3)
+ {
+ tmp_psize = FLASH_PSIZE_WORD;
+ }
+ else
+ {
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+ }
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all sectors */
+ FLASH->CR &= CR_PSIZE_MASK;
+ FLASH->CR |= tmp_psize;
+ FLASH->CR |= FLASH_CR_MER1;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation();
+
+ /* if the erase operation is completed, disable the MER Bit */
+ FLASH->CR &= (~FLASH_CR_MER1);
+
+ }
+ /* Return the Erase Status */
+ return status;
+}
+
+
+/**
+ * @brief Erases all FLASH Sectors in Bank 2.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param VoltageRange: The device voltage range which defines the erase parallelism.
+ * This parameter can be one of the following values:
+ * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
+ * the operation will be done by byte (8-bit)
+ * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
+ * the operation will be done by half word (16-bit)
+ * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
+ * the operation will be done by word (32-bit)
+ * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * the operation will be done by double word (64-bit)
+ *
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+ * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
+{
+ uint32_t tmp_psize = 0x0;
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation();
+ assert_param(IS_VOLTAGERANGE(VoltageRange));
+
+ if(VoltageRange == VoltageRange_1)
+ {
+ tmp_psize = FLASH_PSIZE_BYTE;
+ }
+ else if(VoltageRange == VoltageRange_2)
+ {
+ tmp_psize = FLASH_PSIZE_HALF_WORD;
+ }
+ else if(VoltageRange == VoltageRange_3)
+ {
+ tmp_psize = FLASH_PSIZE_WORD;
+ }
+ else
+ {
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+ }
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all sectors */
+ FLASH->CR &= CR_PSIZE_MASK;
+ FLASH->CR |= tmp_psize;
+ FLASH->CR |= FLASH_CR_MER2;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation();
+
+ /* if the erase operation is completed, disable the MER Bit */
+ FLASH->CR &= (~FLASH_CR_MER2);
}
/* Return the Erase Status */
@@ -676,6 +881,9 @@ FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
(+) void FLASH_OB_Lock(void)
(+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
(+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
+ (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
+ (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
+ (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
(+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
(+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
(+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
@@ -683,9 +891,14 @@ FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
(+) FLASH_Status FLASH_OB_Launch(void)
(+) uint32_t FLASH_OB_GetUser(void)
(+) uint8_t FLASH_OB_GetWRP(void)
- (+) uint8_t FLASH_OB_GetWRP1(void)
+ (+) uint8_t FLASH_OB_GetWRP1(void)
+ (+) uint8_t FLASH_OB_GetPCROP(void)
+ (+) uint8_t FLASH_OB_GetPCROP1(void)
(+) uint8_t FLASH_OB_GetRDP(void)
(+) uint8_t FLASH_OB_GetBOR(void)
+ [..]
+ The following function can be used only for STM32F42xxx/43xxx devices.
+ (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
[..]
Any operation of erase or program should follow these steps:
(#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
@@ -742,7 +955,8 @@ void FLASH_OB_Lock(void)
}
/**
- * @brief Enables or disables the write protection of the desired sectors
+ * @brief Enables or disables the write protection of the desired sectors, for the first
+ * 1 Mb of the Flash
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM4
@@ -781,8 +995,11 @@ void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
}
/**
- * @brief Enables or disables the write protection of the desired sectors
- * @note This function can be used only for STM32F427x/437x devices.
+ * @brief Enables or disables the write protection of the desired sectors, for the second
+ * 1 Mb of the Flash
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
* @note When the memory read out protection is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM4
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
@@ -820,6 +1037,124 @@ void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
}
/**
+ * @brief Select the Protection Mode (SPRMOD).
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices.
+ *
+ * @note After PCROP activation, Option Byte modification is not possible.
+ * Exception made for the global Read Out Protection modification level (level1 to level0)
+ * @note Once SPRMOD bit is active unprotection of a protected sector is not possible
+ *
+ * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+ *
+ * @note Some Precautions should be taken when activating the PCROP feature :
+ * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1
+ * and WRPi = 1 (default value), then the user sector i is read/write protected.
+ * In order to avoid activation of PCROP Mode for undesired sectors, please follow the
+ * below safety sequence :
+ * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function
+ * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
+ * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
+ * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
+ *
+ * @param OB_PCROP: Select the Protection Mode of nWPRi bits
+ * This parameter can be one of the following values:
+ * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
+ * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
+ * @retval None
+ */
+void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
+{
+ uint8_t optiontmp = 0xFF;
+
+ /* Check the parameters */
+ assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
+
+ /* Mask SPRMOD bit */
+ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
+ /* Update Option Byte */
+ *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp);
+
+}
+
+/**
+ * @brief Enables or disables the read/write protection (PCROP) of the desired
+ * sectors, for the first 1 MB of the Flash.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices.
+ *
+ * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
+ * This parameter can be one of the following values:
+ * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for
+ * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and
+ * OB_PCROP_Sector5 for STM32F401xx devices.
+ * @arg OB_PCROP_Sector_All
+ * @param Newstate: new state of the Write Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_PCROP(OB_PCROP));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ status = FLASH_WaitForLastOperation();
+
+ if(status == FLASH_COMPLETE)
+ {
+ if(NewState != DISABLE)
+ {
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
+ }
+ else
+ {
+ *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the read/write protection (PCROP) of the desired
+ * sectors
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
+ * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
+ * This parameter can be one of the following values:
+ * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
+ * @arg OB_PCROP_Sector_All
+ * @param Newstate: new state of the Write Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_PCROP(OB_PCROP));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ status = FLASH_WaitForLastOperation();
+
+ if(status == FLASH_COMPLETE)
+ {
+ if(NewState != DISABLE)
+ {
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
+ }
+ else
+ {
+ *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
+ }
+ }
+}
+
+
+/**
* @brief Sets the read protection level.
* @param OB_RDP: specifies the read protection level.
* This parameter can be one of the following values:
@@ -827,7 +1162,7 @@ void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
* @arg OB_RDP_Level_1: Read protection of the memory
* @arg OB_RDP_Level_2: Full chip protection
*
- * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+ * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
*
* @retval None
*/
@@ -878,8 +1213,15 @@ void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
if(status == FLASH_COMPLETE)
{
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+ /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
+ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
+#endif /* STM32F427_437xx || STM32F429_439xx */
+
+#if defined (STM32F40_41xxx) || defined (STM32F401xx)
/* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
+#endif /* STM32F40_41xxx || STM32F401xx */
/* Update User Option Byte */
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
@@ -887,6 +1229,28 @@ void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
}
/**
+ * @brief Configure the Dual Bank Boot.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
+ * @param OB_BOOT: specifies the Dual Bank Boot Option byte.
+ * This parameter can be one of the following values:
+ * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
+ * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
+ * @retval None
+ */
+void FLASH_OB_BootConfig(uint8_t OB_BOOT)
+{
+ /* Check the parameters */
+ assert_param(IS_OB_BOOT(OB_BOOT));
+
+ /* Set Dual Bank Boot */
+ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
+ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT;
+
+}
+
+/**
* @brief Sets the BOR Level.
* @param OB_BOR: specifies the Option Bytes BOR Reset Level.
* This parameter can be one of the following values:
@@ -951,7 +1315,9 @@ uint16_t FLASH_OB_GetWRP(void)
/**
* @brief Returns the FLASH Write Protection Option Bytes value.
- * @note This function can be used only for STM32F427x/437x devices.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
* @param None
* @retval The FLASH Write Protection Option Bytes value
*/
@@ -962,6 +1328,34 @@ uint16_t FLASH_OB_GetWRP1(void)
}
/**
+ * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx devices.
+ *
+ * @param None
+ * @retval The FLASH PC Read/Write Protection Option Bytes value
+ */
+uint16_t FLASH_OB_GetPCROP(void)
+{
+ /* Return the FLASH PC Read/write protection Register value */
+ return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+}
+
+/**
+ * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx devices.
+ *
+ * @param None
+ * @retval The FLASH PC Read/Write Protection Option Bytes value
+ */
+uint16_t FLASH_OB_GetPCROP1(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
+}
+
+/**
* @brief Returns the FLASH Read Protection level.
* @param None
* @retval FLASH ReadOut Protection Status:
@@ -1049,6 +1443,7 @@ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+ * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42/43xxx and STM32F401xx devices)
* @arg FLASH_FLAG_BSY: FLASH Busy flag
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
@@ -1079,7 +1474,8 @@ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+ * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42/43xxx and STM32F401xx devices)
* @retval None
*/
void FLASH_ClearFlag(uint32_t FLASH_FLAG)
@@ -1095,7 +1491,7 @@ void FLASH_ClearFlag(uint32_t FLASH_FLAG)
* @brief Returns the FLASH Status.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
- * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+ * FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
*/
FLASH_Status FLASH_GetStatus(void)
{
@@ -1113,19 +1509,26 @@ FLASH_Status FLASH_GetStatus(void)
}
else
{
- if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
- {
- flashstatus = FLASH_ERROR_PROGRAM;
- }
- else
+ if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
+ {
+ flashstatus = FLASH_ERROR_RD;
+ }
+ else
{
- if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
+ if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
{
- flashstatus = FLASH_ERROR_OPERATION;
+ flashstatus = FLASH_ERROR_PROGRAM;
}
else
{
- flashstatus = FLASH_COMPLETE;
+ if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
+ {
+ flashstatus = FLASH_ERROR_OPERATION;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPLETE;
+ }
}
}
}
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-09 21:51:54 +0000