1 files changed, 15 insertions, 15 deletions

diff --git a/py/asmarm.c b/py/asmarm.c
index 42724e4d4b..cd346949eb 100644
--- a/py/asmarm.c
+++ b/py/asmarm.c
@@ -39,7 +39,7 @@
 #define SIGNED_FIT24(x) (((x) & 0xff800000) == 0) || (((x) & 0xff000000) == 0xff000000)
 
 // Insert word into instruction flow
-STATIC void emit(asm_arm_t *as, uint op) {
+static void emit(asm_arm_t *as, uint op) {
     uint8_t *c = mp_asm_base_get_cur_to_write_bytes(&as->base, 4);
     if (c != NULL) {
         *(uint32_t *)c = op;
@@ -47,73 +47,73 @@ STATIC void emit(asm_arm_t *as, uint op) {
 }
 
 // Insert word into instruction flow, add "ALWAYS" condition code
-STATIC void emit_al(asm_arm_t *as, uint op) {
+static void emit_al(asm_arm_t *as, uint op) {
     emit(as, op | ASM_ARM_CC_AL);
 }
 
 // Basic instructions without condition code
-STATIC uint asm_arm_op_push(uint reglist) {
+static uint asm_arm_op_push(uint reglist) {
     // stmfd sp!, {reglist}
     return 0x92d0000 | (reglist & 0xFFFF);
 }
 
-STATIC uint asm_arm_op_pop(uint reglist) {
+static uint asm_arm_op_pop(uint reglist) {
     // ldmfd sp!, {reglist}
     return 0x8bd0000 | (reglist & 0xFFFF);
 }
 
-STATIC uint asm_arm_op_mov_reg(uint rd, uint rn) {
+static uint asm_arm_op_mov_reg(uint rd, uint rn) {
     // mov rd, rn
     return 0x1a00000 | (rd << 12) | rn;
 }
 
-STATIC uint asm_arm_op_mov_imm(uint rd, uint imm) {
+static uint asm_arm_op_mov_imm(uint rd, uint imm) {
     // mov rd, #imm
     return 0x3a00000 | (rd << 12) | imm;
 }
 
-STATIC uint asm_arm_op_mvn_imm(uint rd, uint imm) {
+static uint asm_arm_op_mvn_imm(uint rd, uint imm) {
     // mvn rd, #imm
     return 0x3e00000 | (rd << 12) | imm;
 }
 
-STATIC uint asm_arm_op_add_imm(uint rd, uint rn, uint imm) {
+static uint asm_arm_op_add_imm(uint rd, uint rn, uint imm) {
     // add rd, rn, #imm
     return 0x2800000 | (rn << 16) | (rd << 12) | (imm & 0xFF);
 }
 
-STATIC uint asm_arm_op_add_reg(uint rd, uint rn, uint rm) {
+static uint asm_arm_op_add_reg(uint rd, uint rn, uint rm) {
     // add rd, rn, rm
     return 0x0800000 | (rn << 16) | (rd << 12) | rm;
 }
 
-STATIC uint asm_arm_op_sub_imm(uint rd, uint rn, uint imm) {
+static uint asm_arm_op_sub_imm(uint rd, uint rn, uint imm) {
     // sub rd, rn, #imm
     return 0x2400000 | (rn << 16) | (rd << 12) | (imm & 0xFF);
 }
 
-STATIC uint asm_arm_op_sub_reg(uint rd, uint rn, uint rm) {
+static uint asm_arm_op_sub_reg(uint rd, uint rn, uint rm) {
     // sub rd, rn, rm
     return 0x0400000 | (rn << 16) | (rd << 12) | rm;
 }
 
-STATIC uint asm_arm_op_mul_reg(uint rd, uint rm, uint rs) {
+static uint asm_arm_op_mul_reg(uint rd, uint rm, uint rs) {
     // mul rd, rm, rs
     assert(rd != rm);
     return 0x0000090 | (rd << 16) | (rs << 8) | rm;
 }
 
-STATIC uint asm_arm_op_and_reg(uint rd, uint rn, uint rm) {
+static uint asm_arm_op_and_reg(uint rd, uint rn, uint rm) {
     // and rd, rn, rm
     return 0x0000000 | (rn << 16) | (rd << 12) | rm;
 }
 
-STATIC uint asm_arm_op_eor_reg(uint rd, uint rn, uint rm) {
+static uint asm_arm_op_eor_reg(uint rd, uint rn, uint rm) {
     // eor rd, rn, rm
     return 0x0200000 | (rn << 16) | (rd << 12) | rm;
 }
 
-STATIC uint asm_arm_op_orr_reg(uint rd, uint rn, uint rm) {
+static uint asm_arm_op_orr_reg(uint rd, uint rn, uint rm) {
     // orr rd, rn, rm
     return 0x1800000 | (rn << 16) | (rd << 12) | rm;
 }