diff options
Diffstat (limited to 'cc3200/misc/mpsystick.c')
| -rw-r--r-- | cc3200/misc/mpsystick.c | 22 |
1 files changed, 2 insertions, 20 deletions
diff --git a/cc3200/misc/mpsystick.c b/cc3200/misc/mpsystick.c index 21c147449d..05fe4fca76 100644 --- a/cc3200/misc/mpsystick.c +++ b/cc3200/misc/mpsystick.c @@ -58,32 +58,14 @@ void sys_tick_wait_at_least(uint32_t start_tick, uint32_t delay_ms) { // The SysTick timer counts down at HAL_FCPU_HZ, so we can use that knowledge // to grab a microsecond counter. -// // We assume that HAL_GetTick returns milliseconds. uint32_t sys_tick_get_microseconds(void) { mp_uint_t irq_state = disable_irq(); uint32_t counter = SysTickValueGet(); uint32_t milliseconds = HAL_GetTick(); - uint32_t status = (HWREG(NVIC_ST_CTRL)); enable_irq(irq_state); - // It's still possible for the countflag bit to get set if the counter was - // reloaded between reading VAL and reading CTRL. With interrupts disabled - // it definitely takes less than 50 HCLK cycles between reading VAL and - // reading CTRL, so the test (counter > 50) is to cover the case where VAL - // is +ve and very close to zero, and the COUNTFLAG bit is also set. - if ((status & NVIC_ST_CTRL_COUNT) && counter > 50) { - // This means that the HW reloaded VAL between the time we read VAL and the - // time we read CTRL, which implies that there is an interrupt pending - // to increment the tick counter. - milliseconds++; - } - uint32_t load = (HWREG(NVIC_ST_RELOAD)); + uint32_t load = SysTickPeriodGet(); counter = load - counter; // Convert from decrementing to incrementing - - // ((load + 1) / 1000) is the number of counts per microsecond. - // - // counter / ((load + 1) / 1000) scales from the systick clock to microseconds - // and is the same thing as (counter * 1000) / (load + 1) - return milliseconds * 1000 + (counter * 1000) / (load + 1); + return (milliseconds * 1000) + ((counter * 1000) / load); } |