diff options
| -rw-r--r-- | stmhal/hal/f7/src/stm32f7xx_hal_rcc.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c index e131f4ef11..e62c5e0511 100644 --- a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c +++ b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c @@ -981,7 +981,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + // dpgeorge: Adjust the way the arithmetic is done so it retains + // precision for the case that pllm doesn't evenly divide HSE_VALUE. + // Must be sure not to overflow, so divide by 4 first. HSE_VALUE + // should be a multiple of 4 (being a multiple of 100 is enough). + pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4; } else { |