diff options
| author | Damien George <damien.p.george@gmail.com> | 2014-10-26 13:54:31 +0000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2014-10-26 13:54:31 +0000 |
| commit | 480a7ce58f6e5dc6179373f1f8b69d6a5434b2d4 (patch) | |
| tree | 613e678dfd9fbf244332b0a2d3bd22b196974163 /tests/pyb/spi.py.exp | |
| parent | de3c806965f907981d5cb5d49fc139845cd94aba (diff) | |
| download | micropython-480a7ce58f6e5dc6179373f1f8b69d6a5434b2d4.tar.gz micropython-480a7ce58f6e5dc6179373f1f8b69d6a5434b2d4.zip | |
stmhal: Change SPI phase spec to 0,1 to match standard conventions.
Was 1 or 2, now 0 or 1 (respectively). 0 means sample MISO on first
edge, 1 means sample on second edge.
Addresses issue #936.
Diffstat (limited to 'tests/pyb/spi.py.exp')
| -rw-r--r-- | tests/pyb/spi.py.exp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/pyb/spi.py.exp b/tests/pyb/spi.py.exp index 030dfe1b34..68ebbcafb6 100644 --- a/tests/pyb/spi.py.exp +++ b/tests/pyb/spi.py.exp @@ -1,5 +1,5 @@ SPI(1) -SPI(1, SPI.MASTER, baudrate=328125, polarity=1, phase=1, bits=8) +SPI(1, SPI.MASTER, baudrate=328125, polarity=1, phase=0, bits=8) SPI(1, SPI.SLAVE, polarity=1, phase=1, bits=8) b'\xff' b'\xff' |