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| author | Damien George <damien.p.george@gmail.com> | 2015-10-19 14:26:19 +0100 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2015-10-19 14:26:19 +0100 |
| commit | 096d1e4512d6a8fb99e2de3c0c23e2cb88cc2d7a (patch) | |
| tree | 62326722511c7582061dc07508619fd269939e6f /tests/inlineasm/asmshift.py | |
| parent | 949c5c91804655fe257f2444cd7ed5a5e5d9bfa7 (diff) | |
| download | micropython-096d1e4512d6a8fb99e2de3c0c23e2cb88cc2d7a.tar.gz micropython-096d1e4512d6a8fb99e2de3c0c23e2cb88cc2d7a.zip | |
py: Add lsl/lsr/asr opcode support to inline Thumb2 assembler.
Diffstat (limited to 'tests/inlineasm/asmshift.py')
| -rw-r--r-- | tests/inlineasm/asmshift.py | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/tests/inlineasm/asmshift.py b/tests/inlineasm/asmshift.py new file mode 100644 index 0000000000..0df2187347 --- /dev/null +++ b/tests/inlineasm/asmshift.py @@ -0,0 +1,29 @@ +@micropython.asm_thumb +def lsl1(r0): + lsl(r0, r0, 1) +print(hex(lsl1(0x123))) + +@micropython.asm_thumb +def lsl23(r0): + lsl(r0, r0, 23) +print(hex(lsl23(1))) + +@micropython.asm_thumb +def lsr1(r0): + lsr(r0, r0, 1) +print(hex(lsr1(0x123))) + +@micropython.asm_thumb +def lsr31(r0): + lsr(r0, r0, 31) +print(hex(lsr31(0x80000000))) + +@micropython.asm_thumb +def asr1(r0): + asr(r0, r0, 1) +print(hex(asr1(0x123))) + +@micropython.asm_thumb +def asr31(r0): + asr(r0, r0, 31) +print(hex(asr31(0x80000000))) |