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| author | Dave Hylands <dhylands@gmail.com> | 2014-03-12 18:06:26 -0700 |
|---|---|---|
| committer | Dave Hylands <dhylands@gmail.com> | 2014-03-12 18:15:55 -0700 |
| commit | f14b92b9e13c9cb9f54a1d740dbea1eeedeccb5b (patch) | |
| tree | 303a4e00c9612951c8ab3cfbe926121724173fd1 /stmhal/system_stm32f4xx.c | |
| parent | 19438fd30a3184b656221a59062ea32453d0fd16 (diff) | |
| download | micropython-f14b92b9e13c9cb9f54a1d740dbea1eeedeccb5b.tar.gz micropython-f14b92b9e13c9cb9f54a1d740dbea1eeedeccb5b.zip | |
REPl working on UART6 with STMHAL
Diffstat (limited to 'stmhal/system_stm32f4xx.c')
| -rw-r--r-- | stmhal/system_stm32f4xx.c | 60 |
1 files changed, 59 insertions, 1 deletions
diff --git a/stmhal/system_stm32f4xx.c b/stmhal/system_stm32f4xx.c index aa9c984731..8d806041c1 100644 --- a/stmhal/system_stm32f4xx.c +++ b/stmhal/system_stm32f4xx.c @@ -65,6 +65,8 @@ #include "stm32f4xx_hal.h"
+void __fatal_error(const char *msg);
+
/**
* @}
*/
@@ -257,8 +259,64 @@ void SystemCoreClockUpdate(void) }
/**
- * @}
+ * @brief System Clock Configuration
+ * The system Clock is configured as follow :
+ * System Clock source = PLL (HSE)
+ * SYSCLK(Hz) = 168000000
+ * HCLK(Hz) = 168000000
+ * AHB Prescaler = 1
+ * APB1 Prescaler = 4
+ * APB2 Prescaler = 2
+ * HSE Frequency(Hz) = 8000000
+ * PLL_M = 8
+ * PLL_N = 336
+ * PLL_P = 2
+ * PLL_Q = 7
+ * VDD(V) = 3.3
+ * Main regulator output voltage = Scale1 mode
+ * Flash Latency(WS) = 5
+ * @param None
+ * @retval None
*/
+void SystemClock_Config(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable Power Control clock */
+ __PWR_CLK_ENABLE();
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /* Enable HSE Oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 7;
+ if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ __fatal_error("HAL_RCC_OscConfig");
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+ clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
+ {
+ __fatal_error("HAL_RCC_ClockConfig");
+ }
+}
/**
* @}
|