Merge tag 'v1.8.1' into parse-bytecode

Many ESP8266 improvements, enhanced WebREPL, and support for STM32L4 MCUs

This release brings general improvements and bug fixes, and some new
features.  There is now a uerror module for consistent errno handling
across ports, as well as textual names of OS errors that are printed when
an OSError is raised.  There is support for frozen packages, via both
frozen scripts and frozen bytecode.  WebREPL on the ESP8266 is greatly
improved with many bug fixes and now supports an unlimited (or very large)
number of reconnects.  The os module on the ESP8266 now has rename, chdir,
getcwd and stat.  The unix port now includes the ussl module by default.
The stmhal port has support for STM32L4 MCUs including the STM32L476
Discovery board and the LimiFrog board.

README:
- add explicit note that subdirs contain more READMEs
- add "make deplibs" to quick build section
- "quick build": Use "make axtls" after all

CODECONVENTIONS.md:
- describe git commit messages conventions

py core:
- obj: add warning note about get_array return value and GC blocks
- objstr: binary type of str/bytes for buffer protocol is 'B'
- runtime: properly handle passing user mappings to ** keyword args
- repl: if there're no better alternatives, try to complete "import"
- mpz: fix bug with overflowing C-shift in division routine
- mpz: do Python style division/modulo within bignum divmod routine
- mpz: fix mpn_div so that it doesn't modify memory of denominator
- vstr: vstr_null_terminated_str(): Extend string by at most one byte
- vstr: change allocation policy, +16 to requested size, instead of *2
- add mperrno.h file with uPy defined errno constants
- add uerrno module, with errno constants and dict
- parse: add uerrno to list of modules to look for constants in
- mperrno: add EAFNOSUPPORT definition
- repl: fix handling of backslash in quotes when checking continuation
- gc: gc_dump_alloc_table(): Show byte/str and (byte)array objects
- gc: make (byte)array type dumping conditional on these types being enabled
- gc: use '=' char for tail blocks when dumping heap
- mperrno: add some more MP_Exxx constants, related to networking
- moduerrno: add more constants to the errno module
- add mp_errno_to_str() and use it to provide nicer OSError msgs
- objfloat, py/modmath: ensure M_PI and M_E defined
- emitglue: fix build on AArch64 (ARMv8, etc.) related to loading .mpy files
- objexcept: don't convert errno to str in constructor, do it in print
- moduerrno: add EACCES, pretty common error on Unix
- gc: gc_dump_alloc_table(): dump heap offset instead of actual address
- objstr: make dedicated splitlines function, supporting diff newlines
- objstringio: add TODO comment about avoiding copying on .getvalue()
- modstruct: raise ValueError on unsupported format char
- stream: support both "exact size" and "one underlying call" operations
- declare constant data as properly constant
- stream: add mp_stream_close() helper function
- mphal.h: provide default prototypes for mp_hal_delay_us/mp_hal_ticks_us
- rework frozen modules support to support packages
- objstr: implement str.center()
- allow to stat and import frozen mpy files using new frozen "VFS"
- makeqstrdata.py: allow to have double-quote characters in qstrs
- objnamedtuple: allow passing field names as a tuple
- moduerrno: add EEXIST, EISDIR, ECONNREFUSED
- modstruct: allow to have "0s" in struct format

extmod:
- modlwip: convert errno's to use MP_Exxx symbols
- modlwip: rework how Python accept callback is called
- when including extmod headers, prefix path with extmod/
- modwebsocket: add close() method
- modwebrepl: add close() method
- moduos_dupterm: dumpterm subsystem is responsible for closing stream
- modussl: make more compatible with non-default obj representations
- machine_i2c: redo mp_hal_pin macros to use open_drain and od_low
- virtpin: initial implementation of open-ended C-level Pin interface
- vfs_fat: replace text error messages by POSIX error numbers
- vfs_fat: add chdir() method
- vfs_fat: add getcwd() method
- vfs_fat: add vfs.stat() method
- add machine time_pulse_us function (at C and Python level)
- machine: add MICROPY_PY_MACHINE_PULSE config for time_pulse_us

lib:
- timeutils/timeutils: timeutils_mktime may accept negative time values

drivers:
- cc3000: rename timeval to cc3000_timeval, to avoid clash
- add C-level function to read DHT11 and DHT22 devices
- display/ssd1306: update SSD1306_SPI to work with new API

tools:
- make-frozen.py: properly escape hex chars when making C strings
- make-frozen.py: quick fix to support package-modules
- mpy-tool.py: add checks for critical configuration vars
- make-frozen.py: update for latest changes in frozen modules support
- mpy-tool.py: include .py extension in frozen filename
- mpy-tool.py: don't strip directories from the frozen source name
- upgrade upip to 0.7: SSL cert warning, use uerrno, better usage message

tests:
- run-tests: factor out list of supported external boards
- disable memoryview tests that overflow int conversion
- basics/string_splitlines: reinstate feature test for splitlines
- struct1: add testcase for an unknown type char
- add testcase for str.center()
- extmod/vfs_fat_ramdisk: add testcases for chdir(), getcwd()
- misc/recursive_iternext.py: increase depth N from 1000 to 2000
- misc/recursive_iternext.py: provide more fine-grained selection of N
- pyb/rtc: make RTC test on pyboard more reliable by calling init()

mpy-cross:
- add -s option to specify the embedded source filename

unix port:
- mphalport: add mp_hal_delay_us() for consistency with other ports
- enable uerrno module
- add ability to include frozen bytecode in the build
- mpconfigport_coverage.h: add dedicated config file for coverage build
- unix_mphal: implement mp_hal_ticks_us()
- support frozen packages
- Makefile: nanbox build is not compatible with modussl, disable
- enable "ussl" module
- mpconfigport.mk: document MICROPY_STANDALONE make-level option
- Makefile: "make axtls": automatically fetch submodules if missing

windows port:
- enable multi-processor compilation for msvc

stmhal port:
- l4: adapt DMA to be able to support STM32L4 MCU series
- l4: adapt startup code, clock configuration and interrupts
- l4: make CCM/DTCM RAM start-up conditional on MCU type
- l4: add support for machine.sleep on STM32L4 MCUs
- dma: make DAC DMA descriptors conditional on having a DAC
- add board files for LIMIFROG board
- for LIMIFROG board, add early-init function to get to DFU mode
- dma: fix builds for boards with an F4 or F7 but no DAC
- sdcard: fix initialisation of DMA TX so that writes work
- can: allow to get existing CAN obj if constructed without args
- fix clock configuration for STM32L476-discovery; also add I2C2
- convert to use internal errno symbols; enable uerrno module
- for network drivers, convert to use MP_Exxx errno symbols
- led: allow LEDs to be in PWM mode with TIM1 and channels 1-4
- i2c: expose I2CHandle3 for use by custom C code
- sdcard: allow to do unaligned read-from/write-to SD card
- support frozen packages using .mpy files
- moduos: getcwd(): use mp_obj_new_exception_arg1()
- dac: add DAC deinit() method
- uart: fix wrong baudrate calculation for stm32l4 series

esp8266 port:
- scripts/: remove use of pin.PULL_NONE
- scripts/inisetup: don't start WebREPL on boot in master branch
- scripts/: add fill() to NeoPixel
- scripts/webrepl: add optional password argument to webrepl.start()
- scripts/webrepl: add start_foreground() method
- main: bump heap size to 28K
- mpconfigport: reduce various parser-related allocation params
- help: add "sta_if.active(True)" command
- convert to use new MP_Exxx errno symbols
- enable uerrno module, weak linked also as errno
- change to use internal errno's
- moduos.c: addition of the rename method to module uos
- scripts/port_diag: add network diagnostic output
- scripts/webrepl_setup: show password placeholder char
- scripts/webrepl_setup: add max password length check
- README: add a very first start section
- add APA102 serial individually controllable LEDs support
- enable collections.OrderedDict
- main: update _boot module loading for recent frozen modules refactors
- scripts/port_diag: dump network interface IP settings
- esp_mphal: fix NLR buffer leak in call_dupterm_read()
- esp_mphal: handle Ctrl+C from dupterm (e.g. WebREPL)
- esp_mphal: mp_uos_dupterm_deactivate() may raise exception
- add mp_hal_pin_input() and mp_hal_pin_output() functions
- modpybspi: configure pins when initialising an SPI object
- xtirq: add xtirq.h for controlling xtensa irqs
- ets_alt_task: don't run ets_loop_iter if irqs are disabled
- modmachine: add disable_irq and enable_irq functions
- enable DHT C-level driver
- add dht.py script for high-level control of DHT11/DHT22 sensor
- Makefile: document "disable" value for UART_OS
- modnetwork: scan() is only supported by STA when it's enabled
- modnetwork: protect scan() callback against memory errors
- modnetwork: allow to press ctrl-C while scan() is running
- uart: properly initialise UART0 RXD pin in uart_config
- moduos: add chdir() and getcwd() functions
- scripts/ntptime: allow to override NTP server
- modmachine: add machine.time_pulse_us function
- enable MICROPY_PY_IO_FILEIO to get compliant text/binary streams
- moduos.c: add stat() to the module uos of esp8266
- rtc: set RTC user memory length to 0 on first boot
- provide a dedicated variable to disable ets_loop_iter
- modpybrtc: handle RTC overflow

docs:
- machine.UART: filter out unimplemented UART methods from esp8266 docs
- esp8266/quickref: new way to get MAC address
- esp8266/quickstart: remove i2c examples with stop=False
- ustruct: describe supported type codes
- ussl: add basic description of axTLS-based modussl
- esp8266: Include ussl module in the docs
- machine: make disable_irq and enable_irq docs available for all
- library/machine: add documentation for machine.time_pulse_us
- math, cmath: add port availability information
- library/index: add intro paragraph regarding availability of modules
- README: add some hints for PDF docs generation
- wipy/tutorial: add note about screen key bindings on OS X
- esp8266/quickref: update WebREPL section for 1.8.1 release
- esp8266: fix ESP8266 Network tutorial
- esp8266/quickref: use local image of Adafruit Huzzah board
- esp8266/general: add note about RTC overflow

travis:
- install gcc-arm-none-eabi with --force-yes for now

1 files changed, 130 insertions, 10 deletions

diff --git a/stmhal/system_stm32.c b/stmhal/system_stm32.c
index e286a15725..96caa7d36d 100644
--- a/stmhal/system_stm32.c
+++ b/stmhal/system_stm32.c
@@ -108,6 +108,30 @@ void __fatal_error(const char *msg);
   * @{
   */
 
+#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+
+#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
+#define CONFIG_RCC_CR_2ND (RCC_CR_HSEON || RCC_CR_CSSON || RCC_CR_PLLON)
+#define CONFIG_RCC_PLLCFGR (0x24003010)
+
+#elif defined(MCU_SERIES_L4)
+
+#define CONFIG_RCC_CR_1ST (RCC_CR_MSION)
+#define CONFIG_RCC_CR_2ND (RCC_CR_HSEON || RCC_CR_CSSON || RCC_CR_HSION || RCC_CR_PLLON)
+#define CONFIG_RCC_PLLCFGR (0x00001000)
+/*
+ * FIXME Do not know why I have to define these arrays here! they should be defined in the
+ * hal_rcc-file!!
+ *
+ */
+const uint8_t  AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t  APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
+const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
+                                  4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
+#else
+#error Unknown processor
+#endif
+
 /************************* Miscellaneous Configuration ************************/
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
@@ -172,23 +196,28 @@ void SystemInit(void)
     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
   #endif
   /* Reset the RCC clock configuration to the default reset state ------------*/
+
   /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
+  RCC->CR |= CONFIG_RCC_CR_1ST;
 
   /* Reset CFGR register */
   RCC->CFGR = 0x00000000;
 
   /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
+  RCC->CR &= ~ CONFIG_RCC_CR_2ND;
 
   /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
+  RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
 
   /* Reset HSEBYP bit */
   RCC->CR &= (uint32_t)0xFFFBFFFF;
 
   /* Disable all interrupts */
+  #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
   RCC->CIR = 0x00000000;
+  #elif defined(MCU_SERIES_L4)
+  RCC->CIER = 0x00000000;
+  #endif
 
   /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
@@ -204,7 +233,8 @@ void SystemInit(void)
 
 /**
   * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
+  *
+  *         The system Clock is configured for F4/F7 as follows:
   *            System Clock source            = PLL (HSE)
   *            SYSCLK(Hz)                     = 168000000
   *            HCLK(Hz)                       = 168000000
@@ -219,15 +249,39 @@ void SystemInit(void)
   *            VDD(V)                         = 3.3
   *            Main regulator output voltage  = Scale1 mode
   *            Flash Latency(WS)              = 5
+  *
+  *         The system Clock is configured for L4 as follows:
+  *            System Clock source            = PLL (MSI)
+  *            SYSCLK(Hz)                     = 80000000
+  *            HCLK(Hz)                       = 80000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            APB2 Prescaler                 = 1
+  *            MSI Frequency(Hz)              = MSI_VALUE (4000000)
+  *            LSE Frequency(Hz)              = 32768
+  *            PLL_M                          = 1
+  *            PLL_N                          = 40
+  *            PLL_P                          = 7
+  *            PLL_Q                          = 2
+  *            PLL_R                          = 2 <= This is the source for SysClk, not as on F4/7 PLL_P
+  *            Flash Latency(WS)              = 4
   * @param  None
   * @retval None
   *
   * PLL is configured as follows:
   *
-  *     VCO_IN  = HSE / M
-  *     VCO_OUT = HSE / M * N
-  *     PLLCLK  = HSE / M * N / P
-  *     PLL48CK = HSE / M * N / Q
+  *     VCO_IN
+  *         F4/F7 = HSE / M
+  *         L4    = MSI / M
+  *     VCO_OUT
+  *         F4/F7 = HSE / M * N
+  *         L4    = MSI / M * N
+  *     PLLCLK
+  *         F4/F7 = HSE / M * N / P
+  *         L4    = MSI / M * N / R
+  *     PLL48CK
+  *         F4/F7 = HSE / M * N / Q
+  *         L4    = MSI / M * N / Q  USB Clock is obtained over PLLSAI1
   *
   *     SYSCLK = PLLCLK
   *     HCLK   = SYSCLK / AHB_PRESC
@@ -261,6 +315,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
 
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
   /* Enable Power Control clock */
   __PWR_CLK_ENABLE();
 
@@ -268,12 +323,29 @@ void SystemClock_Config(void)
      clocked below the maximum system frequency, to update the voltage scaling value
      regarding system frequency refer to product datasheet.  */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+    #elif defined(MCU_SERIES_L4)
+    /* Enable the LSE Oscillator */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        __fatal_error("HAL_RCC_OscConfig");
+    }
+    #endif
 
     /* Enable HSE Oscillator and activate PLL with HSE as source */
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
     RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+    #elif defined(MCU_SERIES_L4)
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+    RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+    #endif
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
     /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
      clocks dividers */
     RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
@@ -282,6 +354,8 @@ void SystemClock_Config(void)
 #if defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
     #if defined(MCU_SERIES_F7)
     #define FREQ_BKP BKP31R
+    #elif defined(MCU_SERIES_L4)
+    #error Unsupported Processor
     #else
     #define FREQ_BKP BKP19R
     #endif
@@ -319,15 +393,23 @@ void SystemClock_Config(void)
     RCC_ClkInitStruct.AHBCLKDivider = h;  //RCC_SYSCLK_DIV1;
     RCC_ClkInitStruct.APB1CLKDivider = b1; //RCC_HCLK_DIV4;
     RCC_ClkInitStruct.APB2CLKDivider = b2; //RCC_HCLK_DIV2;
-#else
+#else // defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
     RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM;
     RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
     RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP;
     RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ;
+    #if defined(MCU_SERIES_L4)
+    RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR;
+    #endif
 
     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+    #elif defined(MCU_SERIES_L4)
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+    #endif
 #endif
   if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
@@ -358,6 +440,44 @@ void SystemClock_Config(void)
 
   RCC->DCKCFGR2 = 0;
 #endif
+#if defined(MCU_SERIES_L4)
+    // Enable MSI-Hardware auto calibration mode with LSE
+    HAL_RCCEx_EnableMSIPLLMode();
+
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1|RCC_PERIPHCLK_I2C1
+                                              |RCC_PERIPHCLK_USB |RCC_PERIPHCLK_ADC
+                                              |RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_RTC;
+    PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
+    /* PLLSAI is used to clock USB, ADC, I2C1 and RNG. The frequency is
+       HSE(8MHz)/PLLM(2)*PLLSAI1N(24)/PLLSAIQ(2) = 48MHz. See the STM32CubeMx
+       application or the reference manual. */
+    PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLLSAI1;
+    PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+    PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLLSAI1;
+    PeriphClkInitStruct.PLLSAI1.PLLSAI1N = 24;
+    PeriphClkInitStruct.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    PeriphClkInitStruct.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    PeriphClkInitStruct.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK
+                                                 |RCC_PLLSAI1_48M2CLK
+                                                 |RCC_PLLSAI1_ADC1CLK;
+
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+        __fatal_error("HAL_RCCEx_PeriphCLKConfig");
+    }
+
+    __PWR_CLK_ENABLE();
+
+    HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+    HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+#endif
 }
 
 void HAL_MspInit(void) {