diff options
| author | Dave Hylands <dhylands@gmail.com> | 2015-07-28 11:13:33 -0700 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2015-07-30 00:38:32 +0100 |
| commit | 92d4b51ad5d828930334f87d9619a78b5877a384 (patch) | |
| tree | b055ba812bfce720130c6c52272bde38e80a00c9 /stmhal/storage.c | |
| parent | 7e7fb0b7a3d716062281c2366de97a41a1ea87c1 (diff) | |
| download | micropython-92d4b51ad5d828930334f87d9619a78b5877a384.tar.gz micropython-92d4b51ad5d828930334f87d9619a78b5877a384.zip | |
stmhal: Add STM32F7DISC and associated changes.
Diffstat (limited to 'stmhal/storage.c')
| -rw-r--r-- | stmhal/storage.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/stmhal/storage.c b/stmhal/storage.c index 97dfc74b2b..d0567b4fba 100644 --- a/stmhal/storage.c +++ b/stmhal/storage.c @@ -55,6 +55,15 @@ STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k #define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1 #define FLASH_MEM_SEG1_NUM_BLOCKS (128) // sectors 1,2,3,4: 16k+16k+16k+16k(of 64k)=64k +#elif defined(STM32F746xx) + +// The STM32F746 doesn't really have CCRAM, so we use the 64K DTCM for this. + +#define CACHE_MEM_START_ADDR (0x20000000) // DTCM data RAM, 64k +#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of DTCM +#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (224) // sectors 1,2,3,4: 16k+16k+16k+64k=112k + #else #error "no storage support for this MCU" #endif |