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| author | Dave Hylands <dhylands@gmail.com> | 2016-09-27 23:11:36 -0700 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2016-10-04 14:31:19 +1100 |
| commit | 1f433c719b1d29a44c52befdf1476d154ebb3c68 (patch) | |
| tree | e5daed73647319899ca1da9652de51f443e4316e /stmhal/storage.c | |
| parent | bd925b59c3177542fa69c3c95f9f1a40ced18039 (diff) | |
| download | micropython-1f433c719b1d29a44c52befdf1476d154ebb3c68.tar.gz micropython-1f433c719b1d29a44c52befdf1476d154ebb3c68.zip | |
stmhal: Fix linker map for STM32L476 chips.
In particular, this makes the L4 .isr_vector section 16K in size so it's
the same as the F4/F7 MCUs. The patch also moves the L4 filesystem to
the end of flash, which allows for 512K filesystem on the 1Mb devices
like the STM32L476DISC.
Diffstat (limited to 'stmhal/storage.c')
| -rw-r--r-- | stmhal/storage.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/stmhal/storage.c b/stmhal/storage.c index 0c91fa0848..7f910f4e2a 100644 --- a/stmhal/storage.c +++ b/stmhal/storage.c @@ -86,11 +86,14 @@ STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k #elif defined(STM32L476xx) +extern uint8_t _flash_fs_start; +extern uint8_t _flash_fs_end; + // The STM32L476 doesn't have CCRAM, so we use the 32K SRAM2 for this. #define CACHE_MEM_START_ADDR (0x10000000) // SRAM2 data RAM, 32k #define FLASH_SECTOR_SIZE_MAX (0x00800) // 2k max -#define FLASH_MEM_SEG1_START_ADDR (0x08000800) // sector 1 -#define FLASH_MEM_SEG1_NUM_BLOCKS (252) // 1 Block=512 Bytes Reserve 126 kBytes +#define FLASH_MEM_SEG1_START_ADDR ((long)&_flash_fs_start) +#define FLASH_MEM_SEG1_NUM_BLOCKS ((&_flash_fs_end - &_flash_fs_start) / 512) #else #error "no storage support for this MCU" |