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author | Damien George <damien.p.george@gmail.com> | 2017-03-28 12:54:01 +1100 |
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committer | Damien George <damien.p.george@gmail.com> | 2017-03-28 12:54:01 +1100 |
commit | ff927cb106a6a74bd04f729bc0c1fded6955881f (patch) | |
tree | 24e7dc212fe465e172a36432cbebe62f2b2adad9 /stmhal/spi.c | |
parent | 9a1b3da158baf1882777f97212616ca3fe925963 (diff) | |
download | micropython-ff927cb106a6a74bd04f729bc0c1fded6955881f.tar.gz micropython-ff927cb106a6a74bd04f729bc0c1fded6955881f.zip |
stmhal/spi: Clean and/or invalidate D-cache before SPI DMA transfers.
On MCUs with a cache (eg F7) this must be done or else the SPI data that is
transferred is incorrect.
Diffstat (limited to 'stmhal/spi.c')
-rw-r--r-- | stmhal/spi.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/stmhal/spi.c b/stmhal/spi.c index 234d4bab72..0b9674669a 100644 --- a/stmhal/spi.c +++ b/stmhal/spi.c @@ -419,6 +419,7 @@ STATIC void spi_transfer(const pyb_spi_obj_t *self, size_t len, const uint8_t *s dma_init(&tx_dma, self->tx_dma_descr, self->spi); self->spi->hdmatx = &tx_dma; self->spi->hdmarx = NULL; + MP_HAL_CLEAN_DCACHE(src, len); status = HAL_SPI_Transmit_DMA(self->spi, (uint8_t*)src, len); if (status == HAL_OK) { status = spi_wait_dma_finished(self->spi, timeout); @@ -440,7 +441,7 @@ STATIC void spi_transfer(const pyb_spi_obj_t *self, size_t len, const uint8_t *s } dma_init(&rx_dma, self->rx_dma_descr, self->spi); self->spi->hdmarx = &rx_dma; - + MP_HAL_CLEANINVALIDATE_DCACHE(dest, len); status = HAL_SPI_Receive_DMA(self->spi, dest, len); if (status == HAL_OK) { status = spi_wait_dma_finished(self->spi, timeout); @@ -460,6 +461,8 @@ STATIC void spi_transfer(const pyb_spi_obj_t *self, size_t len, const uint8_t *s self->spi->hdmatx = &tx_dma; dma_init(&rx_dma, self->rx_dma_descr, self->spi); self->spi->hdmarx = &rx_dma; + MP_HAL_CLEAN_DCACHE(src, len); + MP_HAL_CLEANINVALIDATE_DCACHE(dest, len); status = HAL_SPI_TransmitReceive_DMA(self->spi, (uint8_t*)src, dest, len); if (status == HAL_OK) { status = spi_wait_dma_finished(self->spi, timeout); |