summaryrefslogtreecommitdiffstatshomepage
path: root/stmhal/dma.h
diff options
context:
space:
mode:
authorDave Hylands <dhylands@gmail.com>2015-12-01 00:42:47 -0800
committerDamien George <damien.p.george@gmail.com>2015-12-02 22:55:57 +0000
commit0077958ad0d278c87620ee8ead9a9aea80f1663d (patch)
treee57c4824ee6c97eff42c4f4bf39934ccea4a3308 /stmhal/dma.h
parentd735278c9f2e14dba51bd75e4152065b81925152 (diff)
downloadmicropython-0077958ad0d278c87620ee8ead9a9aea80f1663d.tar.gz
micropython-0077958ad0d278c87620ee8ead9a9aea80f1663d.zip
stmhal: Put all DMA channel & stream definitions in dma.h
Diffstat (limited to 'stmhal/dma.h')
-rw-r--r--stmhal/dma.h58
1 files changed, 55 insertions, 3 deletions
diff --git a/stmhal/dma.h b/stmhal/dma.h
index 3e62792613..0e751757fd 100644
--- a/stmhal/dma.h
+++ b/stmhal/dma.h
@@ -24,12 +24,64 @@
* THE SOFTWARE.
*/
-//TODO: Put stream/channel defs for i2c/spi/can, etc here
+// These are ordered by DMAx_Stream number, and within a stream by channel
+// number. The duplicate streams are ok as long as they aren't used at the
+// same time.
+//
+// Currently I2C and SPI are synchronous and they call dma_init/dma_deinit
+// around each transfer.
+
+// DMA1 streams
+
+#define DMA_STREAM_I2C1_RX DMA1_Stream0
+#define DMA_CHANNEL_I2C1_RX DMA_CHANNEL_1
+
+#define DMA_STREAM_SPI3_RX DMA1_Stream2
+#define DMA_CHANNEL_SPI3_RX DMA_CHANNEL_0
+
+#define DMA_STREAM_I2C3_RX DMA1_Stream2
+#define DMA_CHANNEL_I2C3_RX DMA_CHANNEL_3
+
+#define DMA_STREAM_I2C2_RX DMA1_Stream2
+#define DMA_CHANNEL_I2C2_RX DMA_CHANNEL_7
+
+#define DMA_STREAM_SPI2_RX DMA1_Stream3
+#define DMA_CHANNEL_SPI2_RX DMA_CHANNEL_0
+
+#define DMA_STREAM_SPI2_TX DMA1_Stream4
+#define DMA_CHANNEL_SPI2_TX DMA_CHANNEL_0
+
+#define DMA_STREAM_I2C3_TX DMA1_Stream4
+#define DMA_CHANNEL_I2C3_TX DMA_CHANNEL_3
+
+#define DMA_STREAM_DAC1 DMA1_Stream5
+#define DMA_CHANNEL_DAC1 DMA_CHANNEL_7
+
+#define DMA_STREAM_DAC2 DMA1_Stream6
+#define DMA_CHANNEL_DAC2 DMA_CHANNEL_7
+
+#define DMA_STREAM_SPI3_TX DMA1_Stream7
+#define DMA_CHANNEL_SPI3_TX DMA_CHANNEL_0
+
+#define DMA_STREAM_I2C1_TX DMA1_Stream7
+#define DMA_CHANNEL_I2C1_TX DMA_CHANNEL_1
+
+#define DMA_STREAM_I2C2_TX DMA1_Stream7
+#define DMA_CHANNEL_I2C2_TX DMA_CHANNEL_7
+
+// DMA2 streams
+
+#define DMA_STREAM_SPI1_RX DMA2_Stream2
+#define DMA_CHANNEL_SPI1_RX DMA_CHANNEL_3
+
#define DMA_STREAM_SDIO_RX DMA2_Stream3
-#define DMA_CHANNEL_SDIO_RX DMA_CHANNEL_4
+#define DMA_CHANNEL_SDIO_RX DMA_CHANNEL_4
+
+#define DMA_STREAM_SPI1_TX DMA2_Stream5
+#define DMA_CHANNEL_SPI1_TX DMA_CHANNEL_3
#define DMA_STREAM_SDIO_TX DMA2_Stream6
-#define DMA_CHANNEL_SDIO_TX DMA_CHANNEL_4
+#define DMA_CHANNEL_SDIO_TX DMA_CHANNEL_4
typedef union {
uint16_t enabled; // Used to test if both counters are == 0