Merge tag 'v1.8.1' into parse-bytecode

Many ESP8266 improvements, enhanced WebREPL, and support for STM32L4 MCUs

This release brings general improvements and bug fixes, and some new
features.  There is now a uerror module for consistent errno handling
across ports, as well as textual names of OS errors that are printed when
an OSError is raised.  There is support for frozen packages, via both
frozen scripts and frozen bytecode.  WebREPL on the ESP8266 is greatly
improved with many bug fixes and now supports an unlimited (or very large)
number of reconnects.  The os module on the ESP8266 now has rename, chdir,
getcwd and stat.  The unix port now includes the ussl module by default.
The stmhal port has support for STM32L4 MCUs including the STM32L476
Discovery board and the LimiFrog board.

README:
- add explicit note that subdirs contain more READMEs
- add "make deplibs" to quick build section
- "quick build": Use "make axtls" after all

CODECONVENTIONS.md:
- describe git commit messages conventions

py core:
- obj: add warning note about get_array return value and GC blocks
- objstr: binary type of str/bytes for buffer protocol is 'B'
- runtime: properly handle passing user mappings to ** keyword args
- repl: if there're no better alternatives, try to complete "import"
- mpz: fix bug with overflowing C-shift in division routine
- mpz: do Python style division/modulo within bignum divmod routine
- mpz: fix mpn_div so that it doesn't modify memory of denominator
- vstr: vstr_null_terminated_str(): Extend string by at most one byte
- vstr: change allocation policy, +16 to requested size, instead of *2
- add mperrno.h file with uPy defined errno constants
- add uerrno module, with errno constants and dict
- parse: add uerrno to list of modules to look for constants in
- mperrno: add EAFNOSUPPORT definition
- repl: fix handling of backslash in quotes when checking continuation
- gc: gc_dump_alloc_table(): Show byte/str and (byte)array objects
- gc: make (byte)array type dumping conditional on these types being enabled
- gc: use '=' char for tail blocks when dumping heap
- mperrno: add some more MP_Exxx constants, related to networking
- moduerrno: add more constants to the errno module
- add mp_errno_to_str() and use it to provide nicer OSError msgs
- objfloat, py/modmath: ensure M_PI and M_E defined
- emitglue: fix build on AArch64 (ARMv8, etc.) related to loading .mpy files
- objexcept: don't convert errno to str in constructor, do it in print
- moduerrno: add EACCES, pretty common error on Unix
- gc: gc_dump_alloc_table(): dump heap offset instead of actual address
- objstr: make dedicated splitlines function, supporting diff newlines
- objstringio: add TODO comment about avoiding copying on .getvalue()
- modstruct: raise ValueError on unsupported format char
- stream: support both "exact size" and "one underlying call" operations
- declare constant data as properly constant
- stream: add mp_stream_close() helper function
- mphal.h: provide default prototypes for mp_hal_delay_us/mp_hal_ticks_us
- rework frozen modules support to support packages
- objstr: implement str.center()
- allow to stat and import frozen mpy files using new frozen "VFS"
- makeqstrdata.py: allow to have double-quote characters in qstrs
- objnamedtuple: allow passing field names as a tuple
- moduerrno: add EEXIST, EISDIR, ECONNREFUSED
- modstruct: allow to have "0s" in struct format

extmod:
- modlwip: convert errno's to use MP_Exxx symbols
- modlwip: rework how Python accept callback is called
- when including extmod headers, prefix path with extmod/
- modwebsocket: add close() method
- modwebrepl: add close() method
- moduos_dupterm: dumpterm subsystem is responsible for closing stream
- modussl: make more compatible with non-default obj representations
- machine_i2c: redo mp_hal_pin macros to use open_drain and od_low
- virtpin: initial implementation of open-ended C-level Pin interface
- vfs_fat: replace text error messages by POSIX error numbers
- vfs_fat: add chdir() method
- vfs_fat: add getcwd() method
- vfs_fat: add vfs.stat() method
- add machine time_pulse_us function (at C and Python level)
- machine: add MICROPY_PY_MACHINE_PULSE config for time_pulse_us

lib:
- timeutils/timeutils: timeutils_mktime may accept negative time values

drivers:
- cc3000: rename timeval to cc3000_timeval, to avoid clash
- add C-level function to read DHT11 and DHT22 devices
- display/ssd1306: update SSD1306_SPI to work with new API

tools:
- make-frozen.py: properly escape hex chars when making C strings
- make-frozen.py: quick fix to support package-modules
- mpy-tool.py: add checks for critical configuration vars
- make-frozen.py: update for latest changes in frozen modules support
- mpy-tool.py: include .py extension in frozen filename
- mpy-tool.py: don't strip directories from the frozen source name
- upgrade upip to 0.7: SSL cert warning, use uerrno, better usage message

tests:
- run-tests: factor out list of supported external boards
- disable memoryview tests that overflow int conversion
- basics/string_splitlines: reinstate feature test for splitlines
- struct1: add testcase for an unknown type char
- add testcase for str.center()
- extmod/vfs_fat_ramdisk: add testcases for chdir(), getcwd()
- misc/recursive_iternext.py: increase depth N from 1000 to 2000
- misc/recursive_iternext.py: provide more fine-grained selection of N
- pyb/rtc: make RTC test on pyboard more reliable by calling init()

mpy-cross:
- add -s option to specify the embedded source filename

unix port:
- mphalport: add mp_hal_delay_us() for consistency with other ports
- enable uerrno module
- add ability to include frozen bytecode in the build
- mpconfigport_coverage.h: add dedicated config file for coverage build
- unix_mphal: implement mp_hal_ticks_us()
- support frozen packages
- Makefile: nanbox build is not compatible with modussl, disable
- enable "ussl" module
- mpconfigport.mk: document MICROPY_STANDALONE make-level option
- Makefile: "make axtls": automatically fetch submodules if missing

windows port:
- enable multi-processor compilation for msvc

stmhal port:
- l4: adapt DMA to be able to support STM32L4 MCU series
- l4: adapt startup code, clock configuration and interrupts
- l4: make CCM/DTCM RAM start-up conditional on MCU type
- l4: add support for machine.sleep on STM32L4 MCUs
- dma: make DAC DMA descriptors conditional on having a DAC
- add board files for LIMIFROG board
- for LIMIFROG board, add early-init function to get to DFU mode
- dma: fix builds for boards with an F4 or F7 but no DAC
- sdcard: fix initialisation of DMA TX so that writes work
- can: allow to get existing CAN obj if constructed without args
- fix clock configuration for STM32L476-discovery; also add I2C2
- convert to use internal errno symbols; enable uerrno module
- for network drivers, convert to use MP_Exxx errno symbols
- led: allow LEDs to be in PWM mode with TIM1 and channels 1-4
- i2c: expose I2CHandle3 for use by custom C code
- sdcard: allow to do unaligned read-from/write-to SD card
- support frozen packages using .mpy files
- moduos: getcwd(): use mp_obj_new_exception_arg1()
- dac: add DAC deinit() method
- uart: fix wrong baudrate calculation for stm32l4 series

esp8266 port:
- scripts/: remove use of pin.PULL_NONE
- scripts/inisetup: don't start WebREPL on boot in master branch
- scripts/: add fill() to NeoPixel
- scripts/webrepl: add optional password argument to webrepl.start()
- scripts/webrepl: add start_foreground() method
- main: bump heap size to 28K
- mpconfigport: reduce various parser-related allocation params
- help: add "sta_if.active(True)" command
- convert to use new MP_Exxx errno symbols
- enable uerrno module, weak linked also as errno
- change to use internal errno's
- moduos.c: addition of the rename method to module uos
- scripts/port_diag: add network diagnostic output
- scripts/webrepl_setup: show password placeholder char
- scripts/webrepl_setup: add max password length check
- README: add a very first start section
- add APA102 serial individually controllable LEDs support
- enable collections.OrderedDict
- main: update _boot module loading for recent frozen modules refactors
- scripts/port_diag: dump network interface IP settings
- esp_mphal: fix NLR buffer leak in call_dupterm_read()
- esp_mphal: handle Ctrl+C from dupterm (e.g. WebREPL)
- esp_mphal: mp_uos_dupterm_deactivate() may raise exception
- add mp_hal_pin_input() and mp_hal_pin_output() functions
- modpybspi: configure pins when initialising an SPI object
- xtirq: add xtirq.h for controlling xtensa irqs
- ets_alt_task: don't run ets_loop_iter if irqs are disabled
- modmachine: add disable_irq and enable_irq functions
- enable DHT C-level driver
- add dht.py script for high-level control of DHT11/DHT22 sensor
- Makefile: document "disable" value for UART_OS
- modnetwork: scan() is only supported by STA when it's enabled
- modnetwork: protect scan() callback against memory errors
- modnetwork: allow to press ctrl-C while scan() is running
- uart: properly initialise UART0 RXD pin in uart_config
- moduos: add chdir() and getcwd() functions
- scripts/ntptime: allow to override NTP server
- modmachine: add machine.time_pulse_us function
- enable MICROPY_PY_IO_FILEIO to get compliant text/binary streams
- moduos.c: add stat() to the module uos of esp8266
- rtc: set RTC user memory length to 0 on first boot
- provide a dedicated variable to disable ets_loop_iter
- modpybrtc: handle RTC overflow

docs:
- machine.UART: filter out unimplemented UART methods from esp8266 docs
- esp8266/quickref: new way to get MAC address
- esp8266/quickstart: remove i2c examples with stop=False
- ustruct: describe supported type codes
- ussl: add basic description of axTLS-based modussl
- esp8266: Include ussl module in the docs
- machine: make disable_irq and enable_irq docs available for all
- library/machine: add documentation for machine.time_pulse_us
- math, cmath: add port availability information
- library/index: add intro paragraph regarding availability of modules
- README: add some hints for PDF docs generation
- wipy/tutorial: add note about screen key bindings on OS X
- esp8266/quickref: update WebREPL section for 1.8.1 release
- esp8266: fix ESP8266 Network tutorial
- esp8266/quickref: use local image of Adafruit Huzzah board
- esp8266/general: add note about RTC overflow

travis:
- install gcc-arm-none-eabi with --force-yes for now

1 files changed, 331 insertions, 94 deletions

diff --git a/stmhal/dma.c b/stmhal/dma.c
index 2255e51601..9f3e87fb9e 100644
--- a/stmhal/dma.c
+++ b/stmhal/dma.c
@@ -33,11 +33,176 @@
 #include "py/obj.h"
 #include "irq.h"
 
-#define NSTREAMS_PER_CONTROLLER_LOG2 (3)
-#define NSTREAMS_PER_CONTROLLER (1 << NSTREAMS_PER_CONTROLLER_LOG2)
+typedef enum {
+    dma_id_not_defined=-1,
+    dma_id_0,
+    dma_id_1,
+    dma_id_2,
+    dma_id_3,
+    dma_id_4,
+    dma_id_5,
+    dma_id_6,
+    dma_id_7,
+    dma_id_8,
+    dma_id_9,
+    dma_id_10,
+    dma_id_11,
+    dma_id_12,
+    dma_id_13,
+    dma_id_14,
+    dma_id_15,
+} dma_id_t;
+
+typedef struct _dma_descr_t {
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    DMA_Stream_TypeDef *instance;
+    #elif defined(MCU_SERIES_L4)
+    DMA_Channel_TypeDef *instance;
+    #else
+    #error "Unsupported Processor"
+    #endif
+    uint32_t sub_instance;
+    uint32_t transfer_direction; // periph to memory or vice-versa
+    dma_id_t id;
+    const DMA_InitTypeDef *init;
+} dma_descr_t;
+
+// Default parameters to dma_init() shared by spi and i2c; Channel and Direction
+// vary depending on the peripheral instance so they get passed separately
+static const DMA_InitTypeDef dma_init_struct_spi_i2c = {
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    .Channel             = 0,
+    #elif defined(MCU_SERIES_L4)
+    .Request             = 0,
+    #endif
+    .Direction           = 0,
+    .PeriphInc           = DMA_PINC_DISABLE,
+    .MemInc              = DMA_MINC_ENABLE,
+    .PeriphDataAlignment = DMA_PDATAALIGN_BYTE,
+    .MemDataAlignment    = DMA_MDATAALIGN_BYTE,
+    .Mode                = DMA_NORMAL,
+    .Priority            = DMA_PRIORITY_LOW,
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    .FIFOMode            = DMA_FIFOMODE_DISABLE,
+    .FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL,
+    .MemBurst            = DMA_MBURST_INC4,
+    .PeriphBurst         = DMA_PBURST_INC4
+    #endif
+};
+
+#if defined(MICROPY_HW_HAS_SDCARD) && MICROPY_HW_HAS_SDCARD
+// Parameters to dma_init() for SDIO tx and rx.
+static const DMA_InitTypeDef dma_init_struct_sdio = {
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    .Channel             = 0,
+    #elif defined(MCU_SERIES_L4)
+    .Request             = 0,
+    #endif
+    .Direction           = 0,
+    .PeriphInc           = DMA_PINC_DISABLE,
+    .MemInc              = DMA_MINC_ENABLE,
+    .PeriphDataAlignment = DMA_PDATAALIGN_WORD,
+    .MemDataAlignment    = DMA_MDATAALIGN_WORD,
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    .Mode                = DMA_PFCTRL,
+    #elif defined(MCU_SERIES_L4)
+    .Mode                = DMA_NORMAL,
+    #endif
+    .Priority            = DMA_PRIORITY_VERY_HIGH,
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    .FIFOMode            = DMA_FIFOMODE_ENABLE,
+    .FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL,
+    .MemBurst            = DMA_MBURST_INC4,
+    .PeriphBurst         = DMA_PBURST_INC4,
+    #endif
+};
+#endif
+
+#if defined(MICROPY_HW_ENABLE_DAC) && MICROPY_HW_ENABLE_DAC
+// Default parameters to dma_init() for DAC tx
+static const DMA_InitTypeDef dma_init_struct_dac = {
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    .Channel             = 0,
+    #elif defined(MCU_SERIES_L4)
+    .Request             = 0,
+    #endif
+    .Direction           = 0,
+    .PeriphInc           = DMA_PINC_DISABLE,
+    .MemInc              = DMA_MINC_ENABLE,
+    .PeriphDataAlignment = DMA_PDATAALIGN_BYTE,
+    .MemDataAlignment    = DMA_MDATAALIGN_BYTE,
+    .Mode                = DMA_NORMAL,
+    .Priority            = DMA_PRIORITY_HIGH,
+    #if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+    .FIFOMode            = DMA_FIFOMODE_DISABLE,
+    .FIFOThreshold       = DMA_FIFO_THRESHOLD_HALFFULL,
+    .MemBurst            = DMA_MBURST_SINGLE,
+    .PeriphBurst         = DMA_PBURST_SINGLE,
+    #endif
+};
+#endif
+
+#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+
 #define NCONTROLLERS            (2)
+#define NSTREAMS_PER_CONTROLLER (8)
 #define NSTREAM                 (NCONTROLLERS * NSTREAMS_PER_CONTROLLER)
 
+#define DMA_SUB_INSTANCE_AS_UINT8(dma_channel) (((dma_channel) & DMA_SxCR_CHSEL) >> 25)
+
+#define DMA1_ENABLE_MASK (0x00ff) // Bits in dma_enable_mask corresponding to DMA1
+#define DMA2_ENABLE_MASK (0xff00) // Bits in dma_enable_mask corresponding to DMA2
+
+// These descriptors are ordered by DMAx_Stream number, and within a stream by channel
+// number. The duplicate streams are ok as long as they aren't used at the same time.
+//
+// Currently I2C and SPI are synchronous and they call dma_init/dma_deinit
+// around each transfer.
+
+// DMA1 streams
+const dma_descr_t dma_I2C_1_RX = { DMA1_Stream0, DMA_CHANNEL_1, DMA_PERIPH_TO_MEMORY, dma_id_0,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_3_RX = { DMA1_Stream2, DMA_CHANNEL_0, DMA_PERIPH_TO_MEMORY, dma_id_2,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_3_RX = { DMA1_Stream2, DMA_CHANNEL_3, DMA_PERIPH_TO_MEMORY, dma_id_2,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_2_RX = { DMA1_Stream2, DMA_CHANNEL_7, DMA_PERIPH_TO_MEMORY, dma_id_2,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_2_RX = { DMA1_Stream3, DMA_CHANNEL_0, DMA_PERIPH_TO_MEMORY, dma_id_3,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_2_TX = { DMA1_Stream4, DMA_CHANNEL_0, DMA_MEMORY_TO_PERIPH, dma_id_4,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_3_TX = { DMA1_Stream4, DMA_CHANNEL_3, DMA_MEMORY_TO_PERIPH, dma_id_4,   &dma_init_struct_spi_i2c };
+#if defined(MICROPY_HW_ENABLE_DAC) && MICROPY_HW_ENABLE_DAC
+const dma_descr_t dma_DAC_1_TX = { DMA1_Stream5, DMA_CHANNEL_7, DMA_MEMORY_TO_PERIPH, dma_id_5,   &dma_init_struct_dac };
+const dma_descr_t dma_DAC_2_TX = { DMA1_Stream6, DMA_CHANNEL_7, DMA_MEMORY_TO_PERIPH, dma_id_6,   &dma_init_struct_dac };
+#endif
+const dma_descr_t dma_SPI_3_TX = { DMA1_Stream7, DMA_CHANNEL_0, DMA_MEMORY_TO_PERIPH, dma_id_7,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_1_TX = { DMA1_Stream7, DMA_CHANNEL_1, DMA_MEMORY_TO_PERIPH, dma_id_7,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_2_TX = { DMA1_Stream7, DMA_CHANNEL_7, DMA_MEMORY_TO_PERIPH, dma_id_7,   &dma_init_struct_spi_i2c };
+/* not preferred streams
+const dma_descr_t dma_SPI_3_RX = { DMA1_Stream0, DMA_CHANNEL_0, DMA_PERIPH_TO_MEMORY, dma_id_0,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_1_TX = { DMA1_Stream6, DMA_CHANNEL_1, DMA_MEMORY_TO_PERIPH, dma_id_6,   &dma_init_struct_spi_i2c };
+*/
+
+// DMA2 streams
+const dma_descr_t dma_SPI_1_RX = { DMA2_Stream2, DMA_CHANNEL_3, DMA_PERIPH_TO_MEMORY, dma_id_10,  &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_5_RX = { DMA2_Stream3, DMA_CHANNEL_2, DMA_PERIPH_TO_MEMORY, dma_id_11,  &dma_init_struct_spi_i2c };
+#if defined(MICROPY_HW_HAS_SDCARD) && MICROPY_HW_HAS_SDCARD
+const dma_descr_t dma_SDIO_0_RX= { DMA2_Stream3, DMA_CHANNEL_4, DMA_PERIPH_TO_MEMORY, dma_id_11,  &dma_init_struct_sdio };
+#endif
+const dma_descr_t dma_SPI_4_RX = { DMA2_Stream3, DMA_CHANNEL_5, DMA_PERIPH_TO_MEMORY, dma_id_11,  &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_5_TX = { DMA2_Stream4, DMA_CHANNEL_2, DMA_MEMORY_TO_PERIPH, dma_id_12,  &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_4_TX = { DMA2_Stream4, DMA_CHANNEL_5, DMA_MEMORY_TO_PERIPH, dma_id_12,  &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_6_TX = { DMA2_Stream5, DMA_CHANNEL_1, DMA_MEMORY_TO_PERIPH, dma_id_13,  &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_1_TX = { DMA2_Stream5, DMA_CHANNEL_3, DMA_MEMORY_TO_PERIPH, dma_id_13,  &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_6_RX = { DMA2_Stream6, DMA_CHANNEL_1, DMA_PERIPH_TO_MEMORY, dma_id_14,  &dma_init_struct_spi_i2c };
+#if defined(MICROPY_HW_HAS_SDCARD) && MICROPY_HW_HAS_SDCARD
+const dma_descr_t dma_SDIO_0_TX= { DMA2_Stream6, DMA_CHANNEL_4, DMA_MEMORY_TO_PERIPH, dma_id_14,  &dma_init_struct_sdio };
+#endif
+/* not preferred streams
+const dma_descr_t dma_SPI_1_TX = { DMA2_Stream3, DMA_CHANNEL_3, DMA_MEMORY_TO_PERIPH, dma_id_11,  &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_1_RX = { DMA2_Stream0, DMA_CHANNEL_3, DMA_PERIPH_TO_MEMORY, dma_id_8,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_4_RX = { DMA2_Stream0, DMA_CHANNEL_4, DMA_PERIPH_TO_MEMORY, dma_id_8,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_4_TX = { DMA2_Stream1, DMA_CHANNEL_4, DMA_MEMORY_TO_PERIPH, dma_id_9,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_5_RX = { DMA2_Stream5, DMA_CHANNEL_7, DMA_PERIPH_TO_MEMORY, dma_id_13,  &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_5_TX = { DMA2_Stream6, DMA_CHANNEL_7, DMA_MEMORY_TO_PERIPH, dma_id_14,  &dma_init_struct_spi_i2c };
+*/
+
 static const uint8_t dma_irqn[NSTREAM] = {
     DMA1_Stream0_IRQn,
     DMA1_Stream1_IRQn,
@@ -57,71 +222,135 @@ static const uint8_t dma_irqn[NSTREAM] = {
     DMA2_Stream7_IRQn,
 };
 
-// Default parameters to dma_init() shared by spi and i2c; Channel and Direction
-// vary depending on the peripheral instance so they get passed separately
-const DMA_InitTypeDef dma_init_struct_spi_i2c = {
-    .Channel             = 0,
-    .Direction           = 0,
-    .PeriphInc           = DMA_PINC_DISABLE,
-    .MemInc              = DMA_MINC_ENABLE,
-    .PeriphDataAlignment = DMA_PDATAALIGN_BYTE,
-    .MemDataAlignment    = DMA_MDATAALIGN_BYTE,
-    .Mode                = DMA_NORMAL,
-    .Priority            = DMA_PRIORITY_LOW,
-    .FIFOMode            = DMA_FIFOMODE_DISABLE,
-    .FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL,
-    .MemBurst            = DMA_MBURST_INC4,
-    .PeriphBurst         = DMA_PBURST_INC4
+#elif defined(MCU_SERIES_L4)
+
+#define NCONTROLLERS            (2)
+#define NSTREAMS_PER_CONTROLLER (7)
+#define NSTREAM                 (NCONTROLLERS * NSTREAMS_PER_CONTROLLER)
+
+#define DMA_SUB_INSTANCE_AS_UINT8(dma_request) (dma_request)
+
+#define DMA1_ENABLE_MASK (0x007f) // Bits in dma_enable_mask corresponfing to DMA1
+#define DMA2_ENABLE_MASK (0x3f80) // Bits in dma_enable_mask corresponding to DMA2
+
+// These descriptors are ordered by DMAx_Channel number, and within a channel by request
+// number. The duplicate streams are ok as long as they aren't used at the same time.
+
+// DMA1 streams
+//const dma_descr_t dma_ADC_1_RX = { DMA1_Channel1, DMA_REQUEST_0, DMA_PERIPH_TO_MEMORY, dma_id_0,   NULL }; // unused
+//const dma_descr_t dma_ADC_2_RX = { DMA1_Channel2, DMA_REQUEST_0, DMA_PERIPH_TO_MEMORY, dma_id_1,   NULL }; // unused
+const dma_descr_t dma_SPI_1_RX = { DMA1_Channel2, DMA_REQUEST_1, DMA_PERIPH_TO_MEMORY, dma_id_1,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_3_TX = { DMA1_Channel2, DMA_REQUEST_3, DMA_MEMORY_TO_PERIPH, dma_id_1,   &dma_init_struct_spi_i2c };
+//const dma_descr_t dma_ADC_3_RX = { DMA1_Channel3, DMA_REQUEST_0, DMA_PERIPH_TO_MEMORY, dma_id_2,   NULL }; // unused
+const dma_descr_t dma_SPI_1_TX = { DMA1_Channel3, DMA_REQUEST_1, DMA_MEMORY_TO_PERIPH, dma_id_2,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_3_RX = { DMA1_Channel3, DMA_REQUEST_3, DMA_PERIPH_TO_MEMORY, dma_id_2,   &dma_init_struct_spi_i2c };
+#if MICROPY_HW_ENABLE_DAC
+const dma_descr_t dma_DAC_1_TX = { DMA1_Channel3, DMA_REQUEST_6, DMA_MEMORY_TO_PERIPH, dma_id_2,   &dma_init_struct_dac };
+#endif
+const dma_descr_t dma_SPI_2_RX = { DMA1_Channel4, DMA_REQUEST_1, DMA_PERIPH_TO_MEMORY, dma_id_3,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_2_TX = { DMA1_Channel4, DMA_REQUEST_3, DMA_MEMORY_TO_PERIPH, dma_id_3,   &dma_init_struct_spi_i2c };
+#if MICROPY_HW_ENABLE_DAC
+const dma_descr_t dma_DAC_2_TX = { DMA1_Channel4, DMA_REQUEST_5, DMA_MEMORY_TO_PERIPH, dma_id_3,   &dma_init_struct_dac };
+#endif
+const dma_descr_t dma_SPI_2_TX = { DMA1_Channel5, DMA_REQUEST_1, DMA_MEMORY_TO_PERIPH, dma_id_4,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_2_RX = { DMA1_Channel5, DMA_REQUEST_3, DMA_PERIPH_TO_MEMORY, dma_id_4,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_1_TX = { DMA1_Channel6, DMA_REQUEST_3, DMA_MEMORY_TO_PERIPH, dma_id_5,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_1_RX = { DMA1_Channel7, DMA_REQUEST_3, DMA_PERIPH_TO_MEMORY, dma_id_6,   &dma_init_struct_spi_i2c };
+
+// DMA2 streams
+const dma_descr_t dma_SPI_3_RX = { DMA2_Channel1, DMA_REQUEST_3, DMA_PERIPH_TO_MEMORY, dma_id_7,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_3_TX = { DMA2_Channel2, DMA_REQUEST_3, DMA_MEMORY_TO_PERIPH, dma_id_8,   &dma_init_struct_spi_i2c };
+/* not preferred streams
+const dma_descr_t dma_ADC_1_RX = { DMA2_Channel3, DMA_REQUEST_0, DMA_PERIPH_TO_MEMORY, dma_id_9,   NULL };
+const dma_descr_t dma_SPI_1_RX = { DMA2_Channel3, DMA_REQUEST_4, DMA_PERIPH_TO_MEMORY, dma_id_9,   &dma_init_struct_spi_i2c };
+const dma_descr_t dma_ADC_2_RX = { DMA2_Channel4, DMA_REQUEST_0, DMA_PERIPH_TO_MEMORY, dma_id_10,  NULL };
+const dma_descr_t dma_DAC_1_TX = { DMA2_Channel4, DMA_REQUEST_3, DMA_MEMORY_TO_PERIPH, dma_id_10,  &dma_init_struct_dac };
+const dma_descr_t dma_SPI_1_TX = { DMA2_Channel4, DMA_REQUEST_4, DMA_MEMORY_TO_PERIPH, dma_id_10,  &dma_init_struct_spi_i2c };
+*/
+#if MICROPY_HW_HAS_SDCARD
+const dma_descr_t dma_SDIO_0_TX= { DMA2_Channel4, DMA_REQUEST_7, DMA_MEMORY_TO_PERIPH, dma_id_10,  &dma_init_struct_sdio };
+#endif
+/* not preferred streams
+const dma_descr_t dma_ADC_3_RX = { DMA2_Channel5, DMA_REQUEST_0, DMA_PERIPH_TO_MEMORY, dma_id_11,  NULL };
+const dma_descr_t dma_DAC_2_TX = { DMA2_Channel5, DMA_REQUEST_3, DMA_MEMORY_TO_PERIPH, dma_id_11,  &dma_init_struct_dac };
+const dma_descr_t dma_SDIO_0_TX= { DMA2_Channel5, DMA_REQUEST_7, DMA_MEMORY_TO_PERIPH, dma_id_11,  &dma_init_struct_sdio };
+const dma_descr_t dma_I2C_1_RX = { DMA2_Channel6, DMA_REQUEST_5, DMA_PERIPH_TO_MEMORY, dma_id_12,  &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_1_TX = { DMA2_Channel7, DMA_REQUEST_5, DMA_MEMORY_TO_PERIPH, dma_id_13,  &dma_init_struct_spi_i2c };
+*/
+
+static const uint8_t dma_irqn[NSTREAM] = {
+    DMA1_Channel1_IRQn,
+    DMA1_Channel2_IRQn,
+    DMA1_Channel3_IRQn,
+    DMA1_Channel4_IRQn,
+    DMA1_Channel5_IRQn,
+    DMA1_Channel6_IRQn,
+    DMA1_Channel7_IRQn,
+    DMA2_Channel1_IRQn,
+    DMA2_Channel2_IRQn,
+    DMA2_Channel3_IRQn,
+    DMA2_Channel4_IRQn,
+    DMA2_Channel5_IRQn,
+    DMA2_Channel6_IRQn,
+    DMA2_Channel7_IRQn,
 };
 
+#endif
+
 static DMA_HandleTypeDef *dma_handle[NSTREAM] = {NULL};
-static uint8_t  dma_last_channel[NSTREAM];
+static uint8_t dma_last_sub_instance[NSTREAM];
 static volatile uint32_t dma_enable_mask = 0;
-
 volatile dma_idle_count_t dma_idle;
 
-#define DMA1_ENABLE_MASK    0x00ff  // Bits in dma_enable_mask corresponfing to DMA1
-#define DMA2_ENABLE_MASK    0xff00  // Bits in dma_enable_mask corresponding to DMA2
 #define DMA_INVALID_CHANNEL 0xff    // Value stored in dma_last_channel which means invalid
 
-#define DMA_CHANNEL_AS_UINT8(dma_channel)   (((dma_channel) & DMA_SxCR_CHSEL) >> 24)
-
-void DMA1_Stream0_IRQHandler(void) { IRQ_ENTER(DMA1_Stream0_IRQn); if (dma_handle[0] != NULL) { HAL_DMA_IRQHandler(dma_handle[0]); } IRQ_EXIT(DMA1_Stream0_IRQn); }
-void DMA1_Stream1_IRQHandler(void) { IRQ_ENTER(DMA1_Stream1_IRQn); if (dma_handle[1] != NULL) { HAL_DMA_IRQHandler(dma_handle[1]); } IRQ_EXIT(DMA1_Stream1_IRQn); }
-void DMA1_Stream2_IRQHandler(void) { IRQ_ENTER(DMA1_Stream2_IRQn); if (dma_handle[2] != NULL) { HAL_DMA_IRQHandler(dma_handle[2]); } IRQ_EXIT(DMA1_Stream2_IRQn); }
-void DMA1_Stream3_IRQHandler(void) { IRQ_ENTER(DMA1_Stream3_IRQn); if (dma_handle[3] != NULL) { HAL_DMA_IRQHandler(dma_handle[3]); } IRQ_EXIT(DMA1_Stream3_IRQn); }
-void DMA1_Stream4_IRQHandler(void) { IRQ_ENTER(DMA1_Stream4_IRQn); if (dma_handle[4] != NULL) { HAL_DMA_IRQHandler(dma_handle[4]); } IRQ_EXIT(DMA1_Stream4_IRQn); }
-void DMA1_Stream5_IRQHandler(void) { IRQ_ENTER(DMA1_Stream5_IRQn); if (dma_handle[5] != NULL) { HAL_DMA_IRQHandler(dma_handle[5]); } IRQ_EXIT(DMA1_Stream5_IRQn); }
-void DMA1_Stream6_IRQHandler(void) { IRQ_ENTER(DMA1_Stream6_IRQn); if (dma_handle[6] != NULL) { HAL_DMA_IRQHandler(dma_handle[6]); } IRQ_EXIT(DMA1_Stream6_IRQn); }
-void DMA1_Stream7_IRQHandler(void) { IRQ_ENTER(DMA1_Stream7_IRQn); if (dma_handle[7] != NULL) { HAL_DMA_IRQHandler(dma_handle[7]); } IRQ_EXIT(DMA1_Stream7_IRQn); }
-void DMA2_Stream0_IRQHandler(void) { IRQ_ENTER(DMA2_Stream0_IRQn); if (dma_handle[8] != NULL) { HAL_DMA_IRQHandler(dma_handle[8]); } IRQ_EXIT(DMA2_Stream0_IRQn); }
-void DMA2_Stream1_IRQHandler(void) { IRQ_ENTER(DMA2_Stream1_IRQn); if (dma_handle[9] != NULL) { HAL_DMA_IRQHandler(dma_handle[9]); } IRQ_EXIT(DMA2_Stream1_IRQn); }
-void DMA2_Stream2_IRQHandler(void) { IRQ_ENTER(DMA2_Stream2_IRQn); if (dma_handle[10] != NULL) { HAL_DMA_IRQHandler(dma_handle[10]); } IRQ_EXIT(DMA2_Stream2_IRQn); }
-void DMA2_Stream3_IRQHandler(void) { IRQ_ENTER(DMA2_Stream3_IRQn); if (dma_handle[11] != NULL) { HAL_DMA_IRQHandler(dma_handle[11]); } IRQ_EXIT(DMA2_Stream3_IRQn); }
-void DMA2_Stream4_IRQHandler(void) { IRQ_ENTER(DMA2_Stream4_IRQn); if (dma_handle[12] != NULL) { HAL_DMA_IRQHandler(dma_handle[12]); } IRQ_EXIT(DMA2_Stream4_IRQn); }
-void DMA2_Stream5_IRQHandler(void) { IRQ_ENTER(DMA2_Stream5_IRQn); if (dma_handle[13] != NULL) { HAL_DMA_IRQHandler(dma_handle[13]); } IRQ_EXIT(DMA2_Stream5_IRQn); }
-void DMA2_Stream6_IRQHandler(void) { IRQ_ENTER(DMA2_Stream6_IRQn); if (dma_handle[14] != NULL) { HAL_DMA_IRQHandler(dma_handle[14]); } IRQ_EXIT(DMA2_Stream6_IRQn); }
-void DMA2_Stream7_IRQHandler(void) { IRQ_ENTER(DMA2_Stream7_IRQn); if (dma_handle[15] != NULL) { HAL_DMA_IRQHandler(dma_handle[15]); } IRQ_EXIT(DMA2_Stream7_IRQn); }
-
 #define DMA1_IS_CLK_ENABLED()   ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0)
 #define DMA2_IS_CLK_ENABLED()   ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0)
 
-static int get_dma_id(DMA_Stream_TypeDef *dma_stream) {
-    int dma_id;
-    if (dma_stream < DMA2_Stream0) {
-        dma_id = dma_stream - DMA1_Stream0;
-    } else {
-        dma_id =  NSTREAMS_PER_CONTROLLER + (dma_stream - DMA2_Stream0);
-    }
-    return dma_id;
-}
+#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
+
+void DMA1_Stream0_IRQHandler(void) { IRQ_ENTER(DMA1_Stream0_IRQn); if (dma_handle[dma_id_0] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_0]); } IRQ_EXIT(DMA1_Stream0_IRQn); }
+void DMA1_Stream1_IRQHandler(void) { IRQ_ENTER(DMA1_Stream1_IRQn); if (dma_handle[dma_id_1] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_1]); } IRQ_EXIT(DMA1_Stream1_IRQn); }
+void DMA1_Stream2_IRQHandler(void) { IRQ_ENTER(DMA1_Stream2_IRQn); if (dma_handle[dma_id_2] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_2]); } IRQ_EXIT(DMA1_Stream2_IRQn); }
+void DMA1_Stream3_IRQHandler(void) { IRQ_ENTER(DMA1_Stream3_IRQn); if (dma_handle[dma_id_3] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_3]); } IRQ_EXIT(DMA1_Stream3_IRQn); }
+void DMA1_Stream4_IRQHandler(void) { IRQ_ENTER(DMA1_Stream4_IRQn); if (dma_handle[dma_id_4] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_4]); } IRQ_EXIT(DMA1_Stream4_IRQn); }
+void DMA1_Stream5_IRQHandler(void) { IRQ_ENTER(DMA1_Stream5_IRQn); if (dma_handle[dma_id_5] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_5]); } IRQ_EXIT(DMA1_Stream5_IRQn); }
+void DMA1_Stream6_IRQHandler(void) { IRQ_ENTER(DMA1_Stream6_IRQn); if (dma_handle[dma_id_6] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_6]); } IRQ_EXIT(DMA1_Stream6_IRQn); }
+void DMA1_Stream7_IRQHandler(void) { IRQ_ENTER(DMA1_Stream7_IRQn); if (dma_handle[dma_id_7] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_7]); } IRQ_EXIT(DMA1_Stream7_IRQn); }
+void DMA2_Stream0_IRQHandler(void) { IRQ_ENTER(DMA2_Stream0_IRQn); if (dma_handle[dma_id_8] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_8]); } IRQ_EXIT(DMA2_Stream0_IRQn); }
+void DMA2_Stream1_IRQHandler(void) { IRQ_ENTER(DMA2_Stream1_IRQn); if (dma_handle[dma_id_9] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_9]); } IRQ_EXIT(DMA2_Stream1_IRQn); }
+void DMA2_Stream2_IRQHandler(void) { IRQ_ENTER(DMA2_Stream2_IRQn); if (dma_handle[dma_id_10] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_10]); } IRQ_EXIT(DMA2_Stream2_IRQn); }
+void DMA2_Stream3_IRQHandler(void) { IRQ_ENTER(DMA2_Stream3_IRQn); if (dma_handle[dma_id_11] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_11]); } IRQ_EXIT(DMA2_Stream3_IRQn); }
+void DMA2_Stream4_IRQHandler(void) { IRQ_ENTER(DMA2_Stream4_IRQn); if (dma_handle[dma_id_12] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_12]); } IRQ_EXIT(DMA2_Stream4_IRQn); }
+void DMA2_Stream5_IRQHandler(void) { IRQ_ENTER(DMA2_Stream5_IRQn); if (dma_handle[dma_id_13] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_13]); } IRQ_EXIT(DMA2_Stream5_IRQn); }
+void DMA2_Stream6_IRQHandler(void) { IRQ_ENTER(DMA2_Stream6_IRQn); if (dma_handle[dma_id_14] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_14]); } IRQ_EXIT(DMA2_Stream6_IRQn); }
+void DMA2_Stream7_IRQHandler(void) { IRQ_ENTER(DMA2_Stream7_IRQn); if (dma_handle[dma_id_15] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_15]); } IRQ_EXIT(DMA2_Stream7_IRQn); }
+
+#elif defined(MCU_SERIES_L4)
+
+void DMA1_Channel1_IRQHandler(void) { IRQ_ENTER(DMA1_Channel1_IRQn); if (dma_handle[dma_id_0] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_0]); } IRQ_EXIT(DMA1_Channel1_IRQn); }
+void DMA1_Channel2_IRQHandler(void) { IRQ_ENTER(DMA1_Channel2_IRQn); if (dma_handle[dma_id_1] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_1]); } IRQ_EXIT(DMA1_Channel2_IRQn); }
+void DMA1_Channel3_IRQHandler(void) { IRQ_ENTER(DMA1_Channel3_IRQn); if (dma_handle[dma_id_2] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_2]); } IRQ_EXIT(DMA1_Channel3_IRQn); }
+void DMA1_Channel4_IRQHandler(void) { IRQ_ENTER(DMA1_Channel4_IRQn); if (dma_handle[dma_id_3] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_3]); } IRQ_EXIT(DMA1_Channel4_IRQn); }
+void DMA1_Channel5_IRQHandler(void) { IRQ_ENTER(DMA1_Channel5_IRQn); if (dma_handle[dma_id_4] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_4]); } IRQ_EXIT(DMA1_Channel5_IRQn); }
+void DMA1_Channel6_IRQHandler(void) { IRQ_ENTER(DMA1_Channel6_IRQn); if (dma_handle[dma_id_5] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_5]); } IRQ_EXIT(DMA1_Channel6_IRQn); }
+void DMA1_Channel7_IRQHandler(void) { IRQ_ENTER(DMA1_Channel7_IRQn); if (dma_handle[dma_id_6] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_6]); } IRQ_EXIT(DMA1_Channel7_IRQn); }
+void DMA2_Channel1_IRQHandler(void) { IRQ_ENTER(DMA2_Channel1_IRQn); if (dma_handle[dma_id_7] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_7]); } IRQ_EXIT(DMA2_Channel1_IRQn); }
+void DMA2_Channel2_IRQHandler(void) { IRQ_ENTER(DMA2_Channel2_IRQn); if (dma_handle[dma_id_8] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_8]); } IRQ_EXIT(DMA2_Channel2_IRQn); }
+void DMA2_Channel3_IRQHandler(void) { IRQ_ENTER(DMA2_Channel3_IRQn); if (dma_handle[dma_id_9] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_9]); } IRQ_EXIT(DMA2_Channel3_IRQn); }
+void DMA2_Channel4_IRQHandler(void) { IRQ_ENTER(DMA2_Channel4_IRQn); if (dma_handle[dma_id_10] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_10]);} IRQ_EXIT(DMA2_Channel4_IRQn); }
+void DMA2_Channel5_IRQHandler(void) { IRQ_ENTER(DMA2_Channel5_IRQn); if (dma_handle[dma_id_11] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_11]);} IRQ_EXIT(DMA2_Channel5_IRQn); }
+void DMA2_Channel6_IRQHandler(void) { IRQ_ENTER(DMA2_Channel6_IRQn); if (dma_handle[dma_id_12] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_12]);} IRQ_EXIT(DMA2_Channel6_IRQn); }
+void DMA2_Channel7_IRQHandler(void) { IRQ_ENTER(DMA2_Channel7_IRQn); if (dma_handle[dma_id_13] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_13]);} IRQ_EXIT(DMA2_Channel7_IRQn); }
+
+#endif
 
 // Resets the idle counter for the DMA controller associated with dma_id.
-static void dma_tickle(int dma_id) {
-    dma_idle.counter[(dma_id >> NSTREAMS_PER_CONTROLLER_LOG2) & 1] = 1;
+static void dma_tickle(dma_id_t dma_id) {
+    dma_idle.counter[(dma_id < NSTREAMS_PER_CONTROLLER) ? 0 : 1] = 1;
 }
 
-static void dma_enable_clock(int dma_id) {
+static void dma_enable_clock(dma_id_t dma_id) {
     // We don't want dma_tick_handler() to turn off the clock right after we
     // enable it, so we need to mark the channel in use in an atomic fashion.
     mp_uint_t irq_state = MICROPY_BEGIN_ATOMIC_SECTION();
@@ -129,7 +358,7 @@ static void dma_enable_clock(int dma_id) {
     dma_enable_mask |= (1 << dma_id);
     MICROPY_END_ATOMIC_SECTION(irq_state);
 
-    if (dma_id <= 7) {
+    if (dma_id < NSTREAMS_PER_CONTROLLER) {
         if (((old_enable_mask & DMA1_ENABLE_MASK) == 0) && !DMA1_IS_CLK_ENABLED()) {
             __DMA1_CLK_ENABLE();
 
@@ -137,7 +366,7 @@ static void dma_enable_clock(int dma_id) {
             // in dma_last_channel (for DMA1) needs to be invalidated.
 
             for (int channel = 0; channel < NSTREAMS_PER_CONTROLLER; channel++) {
-                dma_last_channel[channel] = DMA_INVALID_CHANNEL;
+                dma_last_sub_instance[channel] = DMA_INVALID_CHANNEL;
             }
         }
     } else {
@@ -148,13 +377,13 @@ static void dma_enable_clock(int dma_id) {
             // in dma_last_channel (for DMA1) needs to be invalidated.
 
             for (int channel = NSTREAMS_PER_CONTROLLER; channel < NSTREAM; channel++) {
-                dma_last_channel[channel] = DMA_INVALID_CHANNEL;
+                dma_last_sub_instance[channel] = DMA_INVALID_CHANNEL;
             }
         }
     }
 }
 
-static void dma_disable_clock(int dma_id) {
+static void dma_disable_clock(dma_id_t dma_id) {
     // We just mark the clock as disabled here, but we don't actually disable it.
     // We wait for the timer to expire first, which means that back-to-back
     // transfers don't have to initialize as much.
@@ -162,61 +391,69 @@ static void dma_disable_clock(int dma_id) {
     dma_enable_mask &= ~(1 << dma_id);
 }
 
-void dma_init(DMA_HandleTypeDef *dma, DMA_Stream_TypeDef *dma_stream, const DMA_InitTypeDef *dma_init, uint32_t dma_channel, uint32_t direction, void *data) {
-    int dma_id = get_dma_id(dma_stream);
-    //printf("dma_init(%p, %p(%d), 0x%x, 0x%x, %p)\n", dma, dma_stream, dma_id, (uint)dma_channel, (uint)direction, data);
+void dma_init_handle(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, void *data) {
+    // initialise parameters
+    dma->Instance = dma_descr->instance;
+    dma->Init = *dma_descr->init;
+    dma->Init.Direction = dma_descr->transfer_direction;
+    #if defined(MCU_SERIES_L4)
+    dma->Init.Request = dma_descr->sub_instance;
+    #else
+    dma->Init.Channel = dma_descr->sub_instance;
+    #endif
+    // half of __HAL_LINKDMA(data, xxx, *dma)
+    // caller must implement other half by doing: data->xxx = dma
+    dma->Parent = data;
+}
 
+void dma_init(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, void *data){
     // Some drivers allocate the DMA_HandleTypeDef from the stack
     // (i.e. dac, i2c, spi) and for those cases we need to clear the
     // structure so we don't get random values from the stack)
     memset(dma, 0, sizeof(*dma));
 
-    // set global pointer for IRQ handler
-    dma_handle[dma_id] = dma;
+    if (dma_descr != NULL) {
+        dma_id_t dma_id  = dma_descr->id;
 
-    // initialise parameters
-    dma->Instance = dma_stream;
-    dma->Init = *dma_init;
-    dma->Init.Direction = direction;
-    dma->Init.Channel = dma_channel;
+        dma_init_handle(dma, dma_descr, data);
+        // set global pointer for IRQ handler
+        dma_handle[dma_id] = dma;
 
-    // half of __HAL_LINKDMA(data, xxx, *dma)
-    // caller must implement other half by doing: data->xxx = dma
-    dma->Parent = data;
+        dma_enable_clock(dma_id);
 
-    dma_enable_clock(dma_id);
+        // if this stream was previously configured for this channel/request then we
+        // can skip most of the initialisation
+        uint8_t sub_inst = DMA_SUB_INSTANCE_AS_UINT8(dma_descr->sub_instance);
+        if (dma_last_sub_instance[dma_id] != sub_inst) {
+            dma_last_sub_instance[dma_id] = sub_inst;
 
-    // if this stream was previously configured for this channel then we
-    // can skip most of the initialisation
-    uint8_t channel_uint8 = DMA_CHANNEL_AS_UINT8(dma_channel);
-    if (dma_last_channel[dma_id] == channel_uint8) {
-        goto same_channel;
-    }
-    dma_last_channel[dma_id] = channel_uint8;
+            // reset and configure DMA peripheral
+            if (HAL_DMA_GetState(dma) != HAL_DMA_STATE_RESET) {
+                HAL_DMA_DeInit(dma);
+            }
+            HAL_DMA_Init(dma);
+            HAL_NVIC_SetPriority(dma_irqn[dma_id], IRQ_PRI_DMA, IRQ_SUBPRI_DMA);
+        }
 
-    // reset and configure DMA peripheral
-    if (HAL_DMA_GetState(dma) != HAL_DMA_STATE_RESET) {
-        HAL_DMA_DeInit(dma);
+        HAL_NVIC_EnableIRQ(dma_irqn[dma_id]);
     }
-    HAL_DMA_Init(dma);
-    HAL_NVIC_SetPriority(dma_irqn[dma_id], IRQ_PRI_DMA, IRQ_SUBPRI_DMA);
-
-same_channel:
-    HAL_NVIC_EnableIRQ(dma_irqn[dma_id]);
 }
 
-void dma_deinit(DMA_HandleTypeDef *dma) {
-    int dma_id = get_dma_id(dma->Instance);
-    HAL_NVIC_DisableIRQ(dma_irqn[dma_id]);
-    dma_handle[dma_id] = NULL;
+void dma_deinit(const dma_descr_t *dma_descr) {
+    if (dma_descr != NULL) {
+        HAL_NVIC_DisableIRQ(dma_irqn[dma_descr->id]);
+        dma_handle[dma_descr->id] = NULL;
 
-    dma_disable_clock(dma_id);
+        dma_disable_clock(dma_descr->id);
+    }
 }
 
-void dma_invalidate_channel(DMA_Stream_TypeDef *dma_stream, uint32_t dma_channel) {
-    int dma_id = get_dma_id(dma_stream);
-    if (dma_last_channel[dma_id] == DMA_CHANNEL_AS_UINT8(dma_channel)) {
-        dma_last_channel[dma_id] = DMA_INVALID_CHANNEL;
+void dma_invalidate_channel(const dma_descr_t *dma_descr) {
+    if (dma_descr != NULL) {
+        dma_id_t dma_id = dma_descr->id;
+        if (dma_last_sub_instance[dma_id] == DMA_SUB_INSTANCE_AS_UINT8(dma_descr->sub_instance) ) {
+            dma_last_sub_instance[dma_id] = DMA_INVALID_CHANNEL;
+        }
     }
 }