stm: Re-instate C debugging USART port (disabled by default).

See pyb_usart_global_debug variable.

Also did some work on USB OTG, but nothing working yet.

3 files changed, 147 insertions, 3 deletions

diff --git a/stm/lib/usb_bsp.c b/stm/lib/usb_bsp.c
index c4839bdf96..e88e31db0e 100644
--- a/stm/lib/usb_bsp.c
+++ b/stm/lib/usb_bsp.c
@@ -117,6 +117,17 @@ void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) {
     GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;

     GPIO_Init(GPIOA, &GPIO_InitStructure);

 

+    /*

+    // Configure ID pin (only in host mode)

+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;

+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;

+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;

+    GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;

+    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ;

+    GPIO_Init(GPIOA, &GPIO_InitStructure);

+    GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_OTG_FS);

+    */

+

     RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);

     RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE);

 }

@@ -138,6 +149,84 @@ void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) {
 }

 

 /**

+* @brief  BSP_Drive_VBUS

+*         Drives the Vbus signal through IO

+* @param  state : VBUS states

+* @retval None

+*/

+

+void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev, uint8_t state) {

+    //printf("DriveVBUS %p %u\n", pdev, state);

+    /*

+    On-chip 5 V VBUS generation is not supported. For this reason, a charge pump 

+    or, if 5 V are available on the application board, a basic power switch, must 

+    be added externally to drive the 5 V VBUS line. The external charge pump can 

+    be driven by any GPIO output. When the application decides to power on VBUS 

+    using the chosen GPIO, it must also set the port power bit in the host port 

+    control and status register (PPWR bit in OTG_FS_HPRT).

+

+    Bit 12 PPWR: Port power

+    The application uses this field to control power to this port, and the core 

+    clears this bit on an overcurrent condition.

+    */

+#if 0 // not implemented

+#ifndef USE_USB_OTG_HS

+    if (0 == state) {

+        /* DISABLE is needed on output of the Power Switch */

+        GPIO_SetBits(HOST_POWERSW_PORT, HOST_POWERSW_VBUS);

+    } else {

+        /*ENABLE the Power Switch by driving the Enable LOW */

+        GPIO_ResetBits(HOST_POWERSW_PORT, HOST_POWERSW_VBUS);

+    }

+#endif

+#endif

+}

+

+/**

+  * @brief  USB_OTG_BSP_ConfigVBUS

+  *         Configures the IO for the Vbus and OverCurrent

+  * @param  None

+  * @retval None

+  */

+

+void  USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev) {

+    //printf("ConfigVBUS %p\n", pdev);

+#if 0 // not implemented

+#ifdef USE_USB_OTG_FS   

+  GPIO_InitTypeDef GPIO_InitStructure; 

+  

+#ifdef USE_STM3210C_EVAL

+  RCC_APB2PeriphClockCmd(HOST_POWERSW_PORT_RCC, ENABLE);

+  

+  

+  /* Configure Power Switch Vbus Pin */

+  GPIO_InitStructure.GPIO_Pin = HOST_POWERSW_VBUS;

+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;

+  GPIO_Init(HOST_POWERSW_PORT, &GPIO_InitStructure);

+#else

+  #ifdef USE_USB_OTG_FS  

+  RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOH , ENABLE);  

+  

+  GPIO_InitStructure.GPIO_Pin = HOST_POWERSW_VBUS;

+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;

+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;

+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;

+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;

+  GPIO_Init(HOST_POWERSW_PORT,&GPIO_InitStructure);

+  #endif  

+#endif

+

+  /* By Default, DISABLE is needed on output of the Power Switch */

+  GPIO_SetBits(HOST_POWERSW_PORT, HOST_POWERSW_VBUS);

+  

+  USB_OTG_BSP_mDelay(200);   /* Delay is need for stabilising the Vbus Low 

+  in Reset Condition, when Vbus=1 and Reset-button is pressed by user */

+#endif  

+#endif

+}

+

+/**

 * @brief  USB_OTG_BSP_uDelay

 *         This function provides delay time in micro sec

 * @param  usec : Value of delay required in micro sec

diff --git a/stm/lib/usb_conf.h b/stm/lib/usb_conf.h
index 5e736f91e2..a51a23a84e 100644
--- a/stm/lib/usb_conf.h
+++ b/stm/lib/usb_conf.h
@@ -181,10 +181,65 @@
 /****************** USB OTG MISC CONFIGURATION ********************************/

 #define VBUS_SENSING_ENABLED

 

+/* BEGIN host specific stuff */

+

+/*******************************************************************************

+*                     FIFO Size Configuration in Host mode

+*  

+*  (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or 

+*                             2x (Largest Packet Size / 4) + 1,  If a 

+*                             high-bandwidth channel or multiple isochronous 

+*                             channels are enabled

+*

+*  (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size 

+*      for all supported nonperiodic OUT channels. Typically, a space 

+*      corresponding to two Largest Packet Size is recommended.

+*

+*  (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is 

+*        the largest maximum packet size for all supported periodic OUT channels.

+*        If there is at least one High Bandwidth Isochronous OUT endpoint, 

+*        then the space must be at least two times the maximum packet size for 

+*        that channel.

+*******************************************************************************/

+

+/****************** USB OTG HS CONFIGURATION (for host) ***********************/

+#ifdef USB_OTG_HS_CORE

+ #define RX_FIFO_HS_SIZE                          512

+ #define TXH_NP_HS_FIFOSIZ                        256

+ #define TXH_P_HS_FIFOSIZ                         256

+

+// #define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT

+// #define USB_OTG_HS_SOF_OUTPUT_ENABLED

+

+// #define USB_OTG_INTERNAL_VBUS_ENABLED

+#define USB_OTG_EXTERNAL_VBUS_ENABLED

+

+ #ifdef USE_ULPI_PHY

+  #define USB_OTG_ULPI_PHY_ENABLED

+ #endif

+ #ifdef USE_EMBEDDED_PHY

+   #define USB_OTG_EMBEDDED_PHY_ENABLED

+ #endif

+ #define USB_OTG_HS_INTERNAL_DMA_ENABLED

+// #define USB_OTG_HS_DEDICATED_EP1_ENABLED

+#endif

+

+/****************** USB OTG FS CONFIGURATION (for host) ***********************/

+#ifdef USB_OTG_FS_CORE

+ //#define RX_FIFO_FS_SIZE                          128 // already defined for device (and it's the same)

+ #define TXH_NP_FS_FIFOSIZ                         96

+ #define TXH_P_FS_FIFOSIZ                          96

+

+// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT

+// #define USB_OTG_FS_SOF_OUTPUT_ENABLED

+#endif

+

+/* END host specific stuff */

+

 /****************** USB OTG MODE CONFIGURATION ********************************/

-//#define USE_HOST_MODE

+//#define USE_HOST_MODE // set in Makefile

 #define USE_DEVICE_MODE

-//#define USE_OTG_MODE

+//#define USE_OTG_MODE // set in Makefile

 

 #ifndef USB_OTG_FS_CORE

  #ifndef USB_OTG_HS_CORE

diff --git a/stm/lib/usb_core.c b/stm/lib/usb_core.c
index 4b28c085f2..b0cce88046 100644
--- a/stm/lib/usb_core.c
+++ b/stm/lib/usb_core.c
@@ -617,7 +617,7 @@ USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
   USB_OTG_HCFG_TypeDef            hcfg;

   

 #ifdef USE_OTG_MODE

-  USB_OTG_OTGCTL_TypeDef          gotgctl;

+  USB_OTG_GOTGCTL_TypeDef          gotgctl;

 #endif

   

   uint32_t                        i = 0;