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| author | Damien George <damien.p.george@gmail.com> | 2014-04-21 12:03:09 +0100 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2014-04-21 12:03:09 +0100 |
| commit | 7533700393b4b5d4858e1f5745be4544b2a970cc (patch) | |
| tree | d76bd5859079d5494840670c49fe2886d1fb77e2 /py | |
| parent | 806f4aef9acd9d8990681b9ba73362d995b59417 (diff) | |
| download | micropython-7533700393b4b5d4858e1f5745be4544b2a970cc.tar.gz micropython-7533700393b4b5d4858e1f5745be4544b2a970cc.zip | |
stmhal: Rename USART to UART.
It's really a UART because there is no external clock line (and hence no
synchronous ability, at least in the implementation of this module).
USART should be reserved for a module that has "S"ynchronous capabilities.
Also, UART is shorter and easier to type :)
Diffstat (limited to 'py')
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