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authorDamien George <damien.p.george@gmail.com>2015-06-25 00:21:35 +0100
committerDamien George <damien.p.george@gmail.com>2015-06-25 00:21:35 +0100
commit2110dc5a6dc9de415e8f4dda75262d4b98d1f0a4 (patch)
tree4293916bc3c64fca683c51e8580135c58321734b /docs/reference/asm_thumb2_str.rst
parentaef3846c13d05ddf42e5d6a29042497765f4e871 (diff)
downloadmicropython-2110dc5a6dc9de415e8f4dda75262d4b98d1f0a4.tar.gz
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docs: Add reference for Thumb2 inline assembler.
Thanks to Peter Hinch for contributing this.
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+Store register to memory
+========================
+
+Document conventions
+--------------------
+
+Notation: ``Rt, Rn`` denote ARM registers R0-R7 except where stated. ``immN`` represents an immediate
+value having a width of N bits hence ``imm5`` is constrained to the range 0-31. ``[Rn + imm5]`` is the
+contents of the memory address obtained by adding Rn and the offset ``imm5``. Offsets are measured in
+bytes. These instructions do not affect the condition flags.
+
+Register Store
+--------------
+
+* str(Rt, [Rn, imm7]) ``[Rn + imm7] = Rt`` Store a 32 bit word
+* strb(Rt, [Rn, imm5]) ``[Rn + imm5] = Rt`` Store a byte (b0-b7)
+* strh(Rt, [Rn, imm6]) ``[Rn + imm6] = Rt`` Store a 16 bit half word (b0-b15)
+
+The specified immediate offsets are measured in bytes. Hence in the case of ``str`` the 7 bit value
+enables 32 bit word aligned values to be accessed with a maximum offset of 31 words. In the case of ``strh`` the
+6 bit value enables 16 bit half-word aligned values to be accessed with a maximum offset of 31 half-words.