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author | Damien George <damien.p.george@gmail.com> | 2015-06-25 00:21:35 +0100 |
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committer | Damien George <damien.p.george@gmail.com> | 2015-06-25 00:21:35 +0100 |
commit | 2110dc5a6dc9de415e8f4dda75262d4b98d1f0a4 (patch) | |
tree | 4293916bc3c64fca683c51e8580135c58321734b /docs/reference/asm_thumb2_ldr.rst | |
parent | aef3846c13d05ddf42e5d6a29042497765f4e871 (diff) | |
download | micropython-2110dc5a6dc9de415e8f4dda75262d4b98d1f0a4.tar.gz micropython-2110dc5a6dc9de415e8f4dda75262d4b98d1f0a4.zip |
docs: Add reference for Thumb2 inline assembler.
Thanks to Peter Hinch for contributing this.
Diffstat (limited to 'docs/reference/asm_thumb2_ldr.rst')
-rw-r--r-- | docs/reference/asm_thumb2_ldr.rst | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/docs/reference/asm_thumb2_ldr.rst b/docs/reference/asm_thumb2_ldr.rst new file mode 100644 index 0000000000..16b7729592 --- /dev/null +++ b/docs/reference/asm_thumb2_ldr.rst @@ -0,0 +1,23 @@ +Load register from memory +========================= + +Document conventions +-------------------- + +Notation: ``Rt, Rn`` denote ARM registers R0-R7 except where stated. ``immN`` represents an immediate +value having a width of N bits hence ``imm5`` is constrained to the range 0-31. ``[Rn + immN]`` is the contents +of the memory address obtained by adding Rn and the offset ``immN``. Offsets are measured in +bytes. These instructions affect the condition flags. + +Register Load +------------- + +* ldr(Rt, [Rn, imm7]) ``Rt = [Rn + imm7]`` Load a 32 bit word +* ldrb(Rt, [Rn, imm5]) ``Rt = [Rn + imm5]`` Load a byte +* ldrh(Rt, [Rn, imm6]) ``Rt = [Rn + imm6]`` Load a 16 bit half word + +Where a byte or half word is loaded, it is zero-extended to 32 bits. + +The specified immediate offsets are measured in bytes. Hence in the case of ``ldr`` the 7 bit value +enables 32 bit word aligned values to be accessed with a maximum offset of 31 words. In the case of ``ldrh`` the +6 bit value enables 16 bit half-word aligned values to be accessed with a maximum offset of 31 half-words. |