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| author | Daniel Campora <daniel@wipy.io> | 2015-09-16 14:09:51 +0200 |
|---|---|---|
| committer | Daniel Campora <daniel@wipy.io> | 2015-09-21 22:30:32 +0200 |
| commit | dffa9f6da65cd03e834b2ed3914f40428f72e49f (patch) | |
| tree | 1f2e51f17c511f884db77e47d481c0f9c1b6bed2 /cc3200/misc/mpsystick.c | |
| parent | 660f8613fd8e38863998a9758d97eada0eebc47d (diff) | |
| download | micropython-dffa9f6da65cd03e834b2ed3914f40428f72e49f.tar.gz micropython-dffa9f6da65cd03e834b2ed3914f40428f72e49f.zip | |
cc3200: New SD and RTC API plus os and time modules' extensions.
Diffstat (limited to 'cc3200/misc/mpsystick.c')
| -rw-r--r-- | cc3200/misc/mpsystick.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cc3200/misc/mpsystick.c b/cc3200/misc/mpsystick.c index 7e1cff6ff7..21c147449d 100644 --- a/cc3200/misc/mpsystick.c +++ b/cc3200/misc/mpsystick.c @@ -68,7 +68,7 @@ uint32_t sys_tick_get_microseconds(void) { enable_irq(irq_state); // It's still possible for the countflag bit to get set if the counter was - // reloaded between reading VAL and reading CTRL. With interrupts disabled + // reloaded between reading VAL and reading CTRL. With interrupts disabled // it definitely takes less than 50 HCLK cycles between reading VAL and // reading CTRL, so the test (counter > 50) is to cover the case where VAL // is +ve and very close to zero, and the COUNTFLAG bit is also set. |