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| author | danicampora <daniel@wipy.io> | 2015-11-01 23:17:01 +0100 |
|---|---|---|
| committer | danicampora <daniel@wipy.io> | 2015-11-01 23:33:12 +0100 |
| commit | f67d06194fd56d480809e87dbf761c7973ff2ab7 (patch) | |
| tree | f82137593c4fc721ac6cbddda8d3753bbed51b19 /cc3200/hal/spi.c | |
| parent | d0601b0a1f0bccd28f8b483580f77c21f8998cd1 (diff) | |
| download | micropython-f67d06194fd56d480809e87dbf761c7973ff2ab7.tar.gz micropython-f67d06194fd56d480809e87dbf761c7973ff2ab7.zip | |
cc3200: Fix SPI clock divider calculation.
Diffstat (limited to 'cc3200/hal/spi.c')
| -rw-r--r-- | cc3200/hal/spi.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/cc3200/hal/spi.c b/cc3200/hal/spi.c index 397ac971a6..8c8c678289 100644 --- a/cc3200/hal/spi.c +++ b/cc3200/hal/spi.c @@ -782,15 +782,9 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, } // - // Mask the configurations and set clock divider granularity - // to 1 cycle + // set clock divider granularity to 1 cycle // - ulRegData = (ulRegData & (~(MCSPI_CH0CONF_WL_M | - MCSPI_CH0CONF_EPOL | - MCSPI_CH0CONF_POL | - MCSPI_CH0CONF_PHA | - MCSPI_CH0CONF_TURBO ) | - MCSPI_CH0CONF_CLKG)); + ulRegData |= MCSPI_CH0CONF_CLKG; // // Get the divider value @@ -798,7 +792,7 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, ulDivider = ((ulSPIClk/ulBitRate) - 1); // - // The least significant four bits of the divider is used fo configure + // The least significant four bits of the divider is used to configure // CLKD in MCSPI_CHCONF next eight least significant bits are used to // configure the EXTCLK in MCSPI_CHCTRL // |