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| author | Dave Hylands <dhylands@gmail.com> | 2015-08-15 10:27:35 -0700 |
|---|---|---|
| committer | Dave Hylands <dhylands@gmail.com> | 2015-08-15 10:58:24 -0700 |
| commit | c6f1d47dcbce16efa77a5732f96b0afe74bd1c09 (patch) | |
| tree | 5db7d56919a0dccbb9edac8875767f883aa199c8 | |
| parent | 3179d23cee8d972d93f61e205a359c4ecf0cf54c (diff) | |
| download | micropython-c6f1d47dcbce16efa77a5732f96b0afe74bd1c09.tar.gz micropython-c6f1d47dcbce16efa77a5732f96b0afe74bd1c09.zip | |
stmhal: Enable I & D caches for M7
| -rw-r--r-- | stmhal/system_stm32.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/stmhal/system_stm32.c b/stmhal/system_stm32.c index 3e7e1bc689..22c917adcb 100644 --- a/stmhal/system_stm32.c +++ b/stmhal/system_stm32.c @@ -316,3 +316,13 @@ void SystemClock_Config(void) RCC->DCKCFGR2 = 0; #endif } + +void HAL_MspInit(void) { +#if defined(MCU_SERIES_F7) + /* Enable I-Cache */ + SCB_EnableICache(); + + /* Enable D-Cache */ + SCB_EnableDCache(); +#endif +} |