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| author | Damien George <damien.p.george@gmail.com> | 2017-02-08 10:48:51 +1100 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2017-02-08 10:48:51 +1100 |
| commit | a25aa2bcc3348349d8b1deb8fcdd80b3f10d0550 (patch) | |
| tree | 22c5c6dbf4faa99a4ab484c0db21cad4272459f1 | |
| parent | 21f08524baf11e62384814b7cb8fcd2b5a8998fb (diff) | |
| download | micropython-a25aa2bcc3348349d8b1deb8fcdd80b3f10d0550.tar.gz micropython-a25aa2bcc3348349d8b1deb8fcdd80b3f10d0550.zip | |
py/asmxtensa.h: Explicitly cast args to 32-bits so left-shift is legal.
For archs that have 16-bit pointers, the asmxtensa.h file can give compiler
warnings about left-shift being greater than the width of the type (due to
the inline functions in this header file). Explicitly casting the
constants to uint32_t stops these warnings.
| -rw-r--r-- | py/asmxtensa.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/py/asmxtensa.h b/py/asmxtensa.h index 12083252eb..7db6c0d3dc 100644 --- a/py/asmxtensa.h +++ b/py/asmxtensa.h @@ -73,11 +73,11 @@ // macros for encoding instructions (little endian versions) #define ASM_XTENSA_ENCODE_RRR(op0, op1, op2, r, s, t) \ - (((op2) << 20) | ((op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0)) + ((((uint32_t)op2) << 20) | (((uint32_t)op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0)) #define ASM_XTENSA_ENCODE_RRI4(op0, op1, r, s, t, imm4) \ (((imm4) << 20) | ((op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0)) #define ASM_XTENSA_ENCODE_RRI8(op0, r, s, t, imm8) \ - (((imm8) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0)) + ((((uint32_t)imm8) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0)) #define ASM_XTENSA_ENCODE_RI16(op0, t, imm16) \ (((imm16) << 8) | ((t) << 4) | (op0)) #define ASM_XTENSA_ENCODE_RSR(op0, op1, op2, rs, t) \ @@ -85,7 +85,7 @@ #define ASM_XTENSA_ENCODE_CALL(op0, n, offset) \ (((offset) << 6) | ((n) << 4) | (op0)) #define ASM_XTENSA_ENCODE_CALLX(op0, op1, op2, r, s, m, n) \ - (((op2) << 20) | ((op1) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0)) + ((((uint32_t)op2) << 20) | (((uint32_t)op1) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0)) #define ASM_XTENSA_ENCODE_BRI8(op0, r, s, m, n, imm8) \ (((imm8) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0)) #define ASM_XTENSA_ENCODE_BRI12(op0, s, m, n, imm12) \ |