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| author | Damien George <damien.p.george@gmail.com> | 2015-01-08 22:54:26 +0000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2015-01-08 22:54:26 +0000 |
| commit | 3990dcfcd78017dfada57ff2ca61c2dbcf0b7074 (patch) | |
| tree | 61729190a3266d91a002c21518b8b84351f3bfca | |
| parent | 14fab60bafa81d208b3179b0abae1f5c239dab7a (diff) | |
| download | micropython-3990dcfcd78017dfada57ff2ca61c2dbcf0b7074.tar.gz micropython-3990dcfcd78017dfada57ff2ca61c2dbcf0b7074.zip | |
docs: Add note about maximum frequency of busses.
| -rw-r--r-- | docs/library/pyb.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/docs/library/pyb.rst b/docs/library/pyb.rst index 2fab247592..79caa67d2f 100644 --- a/docs/library/pyb.rst +++ b/docs/library/pyb.rst @@ -113,6 +113,9 @@ Power related functions Supported sysclk frequencies are (in MHz): 8, 16, 24, 30, 32, 36, 40, 42, 48, 54, 56, 60, 64, 72, 84, 96, 108, 120, 144, 168. + The maximum frequency of hclk is 168MHz, of pclk1 is 42MHz, and of pclk2 is + 84MHz. Be sure not to set frequencies above these values. + The hclk, pclk1 and pclk2 frequencies are derived from the sysclk frequency using a prescaler (divider). Supported prescalers for hclk are: 1, 2, 4, 8, 16, 64, 128, 256, 512. Supported prescalers for pclk1 and pclk2 are: 1, 2, |